dec2to4.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dec2to4 is

	port(A	: in std_logic_vector(1 downto 0);
		  Y	: out std_logic_vector(3 downto 0) 
			);
end dec2to4;

architecture Behavioral of dec2to4 is

begin

 process(A) 
	begin
    case A is
        when "00" => Y <= "1110";		  --V zavisimost ot vhodnata kombinaciq e aktiven samo
        when "01" => Y <= "1101";		  --edin ot izhodite. Izhodite sa invertirashti.
        when "10" => Y <= "1011";
        when "11" => Y <= "0111";
        when others => NULL;
    end case;
 end process;

end Behavioral;