fsm.twr

VHDL source code for test machine.

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Release 6.3.03i Trace G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml fsm fsm.ncd -o fsm.twr
fsm.pcf


Design file:              fsm.ncd
Physical constraint file: fsm.pcf
Device,speed:             xc2v40,-5 (PRODUCTION 1.120 2004-11-02, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock SCLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
D<0>        |   -0.113(R)|    0.350(R)|SCLK_BUFGP        |   0.000|
D<1>        |    0.172(R)|    0.065(R)|SCLK_BUFGP        |   0.000|
D<2>        |    0.385(R)|   -0.148(R)|SCLK_BUFGP        |   0.000|
D<3>        |    0.293(R)|   -0.056(R)|SCLK_BUFGP        |   0.000|
D<4>        |    1.840(R)|   -1.603(R)|SCLK_BUFGP        |   0.000|
D<5>        |    0.210(R)|    0.027(R)|SCLK_BUFGP        |   0.000|
D<6>        |    0.410(R)|   -0.173(R)|SCLK_BUFGP        |   0.000|
D<7>        |    1.480(R)|   -1.243(R)|SCLK_BUFGP        |   0.000|
TESTMODE    |    1.117(R)|    0.022(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock SCLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
A<0>        |    7.572(R)|SCLK_BUFGP        |   0.000|
D<0>        |    7.769(R)|SCLK_BUFGP        |   0.000|
D<1>        |    7.769(R)|SCLK_BUFGP        |   0.000|
D<2>        |    8.026(R)|SCLK_BUFGP        |   0.000|
D<3>        |    7.769(R)|SCLK_BUFGP        |   0.000|
D<4>        |    8.026(R)|SCLK_BUFGP        |   0.000|
D<5>        |    8.026(R)|SCLK_BUFGP        |   0.000|
D<6>        |    7.769(R)|SCLK_BUFGP        |   0.000|
D<7>        |    8.026(R)|SCLK_BUFGP        |   0.000|
INDSTATE<0> |    6.057(R)|SCLK_BUFGP        |   0.000|
INDSTATE<1> |    6.056(R)|SCLK_BUFGP        |   0.000|
INDSTATE<2> |    6.056(R)|SCLK_BUFGP        |   0.000|
INDSTATE<3> |    6.057(R)|SCLK_BUFGP        |   0.000|
Indy        |    7.348(R)|SCLK_BUFGP        |   0.000|
OKforCalc   |    7.027(R)|SCLK_BUFGP        |   0.000|
OKforReset  |    7.281(R)|SCLK_BUFGP        |   0.000|
nIndy       |    7.610(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock SCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SCLK           |    3.904|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Jun 26 12:51:26 2007
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Peak Memory Usage: 46 MB