test.tbw

VHDL source code for test machine.

version 3
fsm.vhd
fsm
VHDL
VHDL
test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
SCLK
50000000
50000000
10000000
10000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
A
SCLK
D
SCLK
INDSTATE
SCLK
Indy
SCLK
OKforCalc
SCLK
OKforReset
SCLK
SDATA
SCLK
START
SCLK
TESTMODE
SCLK
nIndy
SCLK
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
INDSTATE_DIFF
Indy_DIFF
OKforCalc_DIFF
OKforReset_DIFF
nIndy_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
SCLK
START
TESTMODE
Indy
OKforCalc
OKforReset
nIndy
INDSTATE
SDATA
A
D
SIGNAL_ORDER_END
-X-X-X-