testmachine.twr

VHDL source code for test machine.

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Release 6.3.03i Trace G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml testmachine
testmachine.ncd -o testmachine.twr testmachine.pcf


Design file:              testmachine.ncd
Physical constraint file: testmachine.pcf
Device,speed:             xc2v40,-5 (PRODUCTION 1.120 2004-11-02, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock SCLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
D<0>        |    2.209(R)|   -1.995(R)|SCLK_BUFGP        |   0.000|
D<1>        |    1.661(R)|   -1.447(R)|SCLK_BUFGP        |   0.000|
D<2>        |    0.745(R)|   -0.531(R)|SCLK_BUFGP        |   0.000|
D<3>        |    1.104(R)|   -0.890(R)|SCLK_BUFGP        |   0.000|
D<4>        |    1.997(R)|   -1.783(R)|SCLK_BUFGP        |   0.000|
D<5>        |    1.841(R)|   -1.627(R)|SCLK_BUFGP        |   0.000|
D<6>        |    1.551(R)|   -1.337(R)|SCLK_BUFGP        |   0.000|
D<7>        |    1.832(R)|   -1.618(R)|SCLK_BUFGP        |   0.000|
TESTMODE    |    1.652(R)|    0.429(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock SCLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
A<0>        |    7.268(R)|SCLK_BUFGP        |   0.000|
INDSTATE<0> |    6.056(R)|SCLK_BUFGP        |   0.000|
INDSTATE<1> |    6.066(R)|SCLK_BUFGP        |   0.000|
INDSTATE<2> |    6.056(R)|SCLK_BUFGP        |   0.000|
INDSTATE<3> |    6.057(R)|SCLK_BUFGP        |   0.000|
OKforCalc   |    7.028(R)|SCLK_BUFGP        |   0.000|
OKforReset  |    7.309(R)|SCLK_BUFGP        |   0.000|
RESET       |    7.288(R)|SCLK_BUFGP        |   0.000|
ResetCalc   |    7.562(R)|SCLK_BUFGP        |   0.000|
ResetIndy   |    7.030(R)|SCLK_BUFGP        |   0.000|
WR          |    7.021(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock SCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SCLK           |    3.417|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Jun 26 13:05:46 2007
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Peak Memory Usage: 46 MB