test1.mdo

VHDL source code for test machine.

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Map Simulation
##
vlib work
## Compile Post-Map Model for Module fsm
vcom -87 -explicit  fsm_map.vhd
vcom -93 -explicit  test1.map_vhw
vsim -t 1ps -sdfmax /UUT=fsm_map.sdf  -lib work test1
do test1.udo
view wave
add wave *
view structure
view signals
run -all
## End