project.par_nlf

VHDL source code for test machine.

Release 6.3.03i - netgen G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "project.ncd".
   "project" is an NCD, version 2.38, device xc2v40, package fg256, speed -5
Loading device for application netgen from file '2v40.nph' in environment
C:/Xilinx.
The STEPPING level for this design is 1.
Loading constraints from file "project.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist project_timesim.vhd ...
Writing VHDL SDF file project_timesim.sdf ...
Total memory usage is 55976 kilobytes