indicator.par

VHDL source code for test machine.

Release 6.3.03i Par G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

VANCHETO::  Tue Jun 26 13:01:21 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 indicator_map.ncd
indicator.ncd indicator.pcf 


Constraints file: indicator.pcf

Loading device database for application Par from file "indicator_map.ncd".
   "indicator" is an NCD, version 2.38, device xc2v40, package fg256, speed -5
Loading device for application Par from file '2v40.nph' in environment
C:/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.120 2004-11-02.


Device utilization summary:

   Number of External IOBs             4 out of 88      4%
      Number of LOCed External IOBs    0 out of 4       0%

   Number of SLICEs                   12 out of 256     4%

   Number of BUFGMUXs                  1 out of 16      6%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.2

Phase 2.2 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98a10b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file indicator.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 86 unrouted;       REAL time: 0 secs 

Phase 2: 73 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|      CLK_IN_BUFGP       | BUFGMUX7P| No   |   12 |  0.003     |  0.572      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 34


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.279
   The MAXIMUM PIN DELAY IS:                               1.044
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.292

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          85           1           0           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file indicator.ncd.


PAR done.