testmachine1.tdo

VHDL source code for test machine.

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module fsm
vcom -87 -explicit  fsm_timesim.vhd
vcom -93 -explicit  testMachine1.timesim_vhw
vsim -t 1ps -sdfmax /UUT=fsm_timesim.sdf  -lib work testMachine1
do testMachine1.udo
view wave
add wave *
view structure
view signals
run -all
## End