indicator.twr

VHDL source code for test machine.

--------------------------------------------------------------------------------
Release 6.3.03i Trace G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml indicator indicator.ncd
-o indicator.twr indicator.pcf


Design file:              indicator.ncd
Physical constraint file: indicator.pcf
Device,speed:             xc2v40,-5 (PRODUCTION 1.120 2004-11-02, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock CLK_IN to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Indy        |    7.028(R)|CLK_IN_BUFGP      |   0.000|
nIndy       |    7.290(R)|CLK_IN_BUFGP      |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK_IN
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_IN         |    3.904|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Jun 26 13:01:24 2007
--------------------------------------------------------------------------------

Peak Memory Usage: 46 MB