project_timesim.vhd

VHDL source code for test machine.

    )
    port map (
      I => REG_OUT_2_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_2_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_2_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_2_1
    );
  REG_OUT_2_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_2_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_2_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_2_OUTPUT_OFF_OFF1_RSTAND_67 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_2_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_3_OUTPUT_OTCLK1INV_68 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_3_OUTPUT_OTCLK1INV
    );
  REG_OUT_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_3_1,
      O => REG_OUT_3_O
    );
  REG_OUT_3_OUTPUT_OFF_O1INV_69 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(3),
      O => REG_OUT_3_OUTPUT_OFF_O1INV
    );
  reg_Q_3_1_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_3_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_3_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_3_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_3_1
    );
  REG_OUT_3_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_3_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_3_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_3_OUTPUT_OFF_OFF1_RSTAND_71 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_3_OUTPUT_OFF_OFF1_RSTAND
    );
  D_2_OUTPUT_OTCLK1INV_72 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_2_OUTPUT_OTCLK1INV
    );
  D_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(2),
      O => D_2_O
    );
  D_2_OUTPUT_OFF_O1INV_73 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(2),
      O => D_2_OUTPUT_OFF_O1INV
    );
  reg_Q_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_2_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_2_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_2_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(2)
    );
  D_2_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_2_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_2_OUTPUT_OFF_OFF1_RST
    );
  D_2_OUTPUT_OFF_OFF1_RSTAND_74 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_2_OUTPUT_OFF_OFF1_RSTAND
    );
  D_3_OUTPUT_OTCLK1INV_75 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_3_OUTPUT_OTCLK1INV
    );
  D_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(3),
      O => D_3_O
    );
  D_3_OUTPUT_OFF_O1INV_76 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(3),
      O => D_3_OUTPUT_OFF_O1INV
    );
  D_4_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_4_OUTPUT_OFF_OSR_USED,
      I1 => GSR,
      O => D_4_OUTPUT_OFF_OFF1_RST
    );
  reg_Q_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_4_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_4_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_4_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(4)
    );
  D_4_OUTPUT_OFF_O1INV_77 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(4),
      O => D_4_OUTPUT_OFF_O1INV
    );
  D_4_OUTPUT_OFF_OSR_USED_78 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_4_OUTPUT_OFF_OSR_USED
    );
  D_4_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(4),
      O => D_4_O
    );
  D_4_OUTPUT_OTCLK1INV_79 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_4_OUTPUT_OTCLK1INV
    );
  reg_Q_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_3_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_3_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_3_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(3)
    );
  D_3_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_3_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_3_OUTPUT_OFF_OFF1_RST
    );
  D_3_OUTPUT_OFF_OFF1_RSTAND_80 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_3_OUTPUT_OFF_OFF1_RSTAND
    );
  D_6_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(6),
      O => D_6_O
    );
  D_6_OUTPUT_OFF_O1INV_81 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(6),
      O => D_6_OUTPUT_OFF_O1INV
    );
  reg_Q_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_6_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_6_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_6_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(6)
    );
  D_6_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_6_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_6_OUTPUT_OFF_OFF1_RST
    );
  D_6_OUTPUT_OFF_OFF1_RSTAND_82 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_6_OUTPUT_OFF_OFF1_RSTAND
    );
  D_7_OUTPUT_OTCLK1INV_83 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_7_OUTPUT_OTCLK1INV
    );
  D_7_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(7),
      O => D_7_O
    );
  D_7_OUTPUT_OFF_O1INV_84 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(7),
      O => D_7_OUTPUT_OFF_O1INV
    );
  reg_Q_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_7_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_7_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_7_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(7)
    );
  D_7_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_7_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_7_OUTPUT_OFF_OFF1_RST
    );
  D_7_OUTPUT_OFF_OFF1_RSTAND_85 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_7_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_0_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_0_OUTPUT_OFF_OSR_USED,
      I1 => GSR,
      O => REG_OUT_0_OUTPUT_OFF_OFF1_RST
    );
  reg_Q_0_1_86 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_0_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_0_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_0_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_0_1
    );
  REG_OUT_0_OUTPUT_OFF_O1INV_87 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(0),
      O => REG_OUT_0_OUTPUT_OFF_O1INV
    );
  REG_OUT_0_OUTPUT_OFF_OSR_USED_88 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_0_OUTPUT_OFF_OSR_USED
    );
  REG_OUT_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_0_1,
      O => REG_OUT_0_O
    );
  REG_OUT_0_OUTPUT_OTCLK1INV_89 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_0_OUTPUT_OTCLK1INV
    );
  REG_OUT_6_OUTPUT_OTCLK1INV_90 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_6_OUTPUT_OTCLK1INV
    );
  REG_OUT_6_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_6_1,
      O => REG_OUT_6_O
    );
  REG_OUT_6_OUTPUT_OFF_O1INV_91 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(6),
      O => REG_OUT_6_OUTPUT_OFF_O1INV
    );
  reg_Q_6_1_92 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_6_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_6_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_6_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_6_1
    );
  REG_OUT_6_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_6_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_6_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_6_OUTPUT_OFF_OFF1_RSTAND_93 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_6_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_7_OUTPUT_OTCLK1INV_94 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_7_OUTPUT_OTCLK1INV
    );
  REG_OUT_7_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_7_1,
      O => REG_OUT_7_O
    );
  REG_OUT_7_OUTPUT_OFF_O1INV_95 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(7),
      O => REG_OUT_7_OUTPUT_OFF_O1INV
    );
  reg_Q_7_1_96 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_7_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_7_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_7_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_7_1
    );
  REG_OUT_7_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_7_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_7_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_7_OUTPUT_OFF_OFF1_RSTAND_97 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_7_OUTPUT_OFF_OFF1_RSTAND
    );
  or2_D_OUT1 : X_LUT4
    generic map(
      INIT => X"FFAF"
    )
    port map (
      ADR0 => A_1_IBUF,
      ADR1 => VCC,
      ADR2 => A_0_IBUF,
      ADR3 => RD_IBUF,
      O => sreg_REG_0_N62_G
    );
  sreg_REG_0_N621 : X_LUT4
    generic map(
      INIT => X"01FF"
    )
    port map (
      ADR0 => A_1_IBUF,
      ADR1 => WR_IBUF,
      ADR2 => A_0_IBUF,
      ADR3 => RESET_IBUF,
      O => sreg_REG_0_N62_F
    );
  sreg_REG_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_8_DXMUX,
      CE => VCC,
      CLK => sreg_REG_8_CLKINV,
      SET => GND,
      RST => sreg_REG_8_FFX_RST,
      O => sreg_REG(8)
    );
  sreg_REG_8_FFX_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_8_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_8_FFX_RST
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  A_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0_INBUF,
      O => A_0_IBUF
    );
  A_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_1_INBUF,
      O => A_1_IBUF
    );
  RD_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RD_INBUF,
      O => RD_IBUF
    );
  IRQ_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => IRQ_O
    );
  SCLK_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_INBUF,
      O => SCLK_BUFGP_IBUFG
    );
  WR_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => WR_INBUF,
      O => WR_IBUF
    );
  D_0_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_0_T
    );
  RESET_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET_INBUF,
      O => RESET_IBUF
    );
  D_1_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_1_T
    );
  D_5_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_5_T
    );
  D_6_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_6_T
    );
  D_2_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_2_T
    );
  D_3_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_3_T
    );
  D_4_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_4_T
    );
  D_7_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OR2_OUT,
      O => D_7_T
    );
  NlwBlock_project_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_project_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;