project_timesim.vhd

VHDL source code for test machine.

      S => SCLK_BUFGP_BUFG_S_INVNOT,
      O => SCLK_BUFGP,
      GSR => GSR
    );
  SCLK_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => SCLK_BUFGP_BUFG_S_INVNOT
    );
  sreg_REG_0_N62_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62_F,
      O => sreg_REG_0_N62
    );
  sreg_REG_0_N62_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62_G,
      O => OR2_OUT
    );
  sreg_REG_2_DXMUX_24 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(1),
      O => sreg_REG_2_DXMUX
    );
  sreg_REG_2_DYMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(0),
      O => sreg_REG_2_DYMUX
    );
  sreg_REG_2_SRFFMUX_26 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => sreg_REG_2_SRFFMUX
    );
  sreg_REG_2_CLKINV_27 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => sreg_REG_2_CLKINV
    );
  sreg_REG_4_DXMUX_28 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(3),
      O => sreg_REG_4_DXMUX
    );
  sreg_REG_4_DYMUX_29 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(2),
      O => sreg_REG_4_DYMUX
    );
  sreg_REG_4_SRFFMUX_30 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => sreg_REG_4_SRFFMUX
    );
  sreg_REG_4_CLKINV_31 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => sreg_REG_4_CLKINV
    );
  sreg_REG_6_DXMUX_32 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(5),
      O => sreg_REG_6_DXMUX
    );
  sreg_REG_6_DYMUX_33 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(4),
      O => sreg_REG_6_DYMUX
    );
  sreg_REG_6_SRFFMUX_34 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => sreg_REG_6_SRFFMUX
    );
  sreg_REG_6_CLKINV_35 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => sreg_REG_6_CLKINV
    );
  D_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(0),
      O => D_0_O
    );
  D_0_OUTPUT_OFF_O1INV_36 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(0),
      O => D_0_OUTPUT_OFF_O1INV
    );
  sreg_REG_8_DXMUX_37 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(7),
      O => sreg_REG_8_DXMUX
    );
  sreg_REG_8_DYMUX_38 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(6),
      O => sreg_REG_8_DYMUX
    );
  sreg_REG_8_SRFFMUX_39 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => sreg_REG_8_SRFFMUX
    );
  sreg_REG_8_CLKINV_40 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => sreg_REG_8_CLKINV
    );
  reg_Q_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_0_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_0_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_0_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(0)
    );
  D_0_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_0_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_0_OUTPUT_OFF_OFF1_RST
    );
  D_0_OUTPUT_OFF_OFF1_RSTAND_41 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_0_OUTPUT_OFF_OFF1_RSTAND
    );
  D_1_OUTPUT_OTCLK1INV_42 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_1_OUTPUT_OTCLK1INV
    );
  D_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(1),
      O => D_1_O
    );
  D_1_OUTPUT_OFF_O1INV_43 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(1),
      O => D_1_OUTPUT_OFF_O1INV
    );
  reg_Q_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_1_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_1_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_1_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(1)
    );
  D_1_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_1_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_1_OUTPUT_OFF_OFF1_RST
    );
  D_1_OUTPUT_OFF_OFF1_RSTAND_44 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_1_OUTPUT_OFF_OFF1_RSTAND
    );
  sreg_REG_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_2_DYMUX,
      CE => VCC,
      CLK => sreg_REG_2_CLKINV,
      SET => GND,
      RST => sreg_REG_2_FFY_RST,
      O => sreg_REG(1)
    );
  sreg_REG_2_FFY_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_2_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_2_FFY_RST
    );
  sreg_REG_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_2_DXMUX,
      CE => VCC,
      CLK => sreg_REG_2_CLKINV,
      SET => GND,
      RST => sreg_REG_2_FFX_RST,
      O => sreg_REG(2)
    );
  sreg_REG_2_FFX_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_2_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_2_FFX_RST
    );
  sreg_REG_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_4_DYMUX,
      CE => VCC,
      CLK => sreg_REG_4_CLKINV,
      SET => GND,
      RST => sreg_REG_4_FFY_RST,
      O => sreg_REG(3)
    );
  sreg_REG_4_FFY_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_4_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_4_FFY_RST
    );
  sreg_REG_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_4_DXMUX,
      CE => VCC,
      CLK => sreg_REG_4_CLKINV,
      SET => GND,
      RST => sreg_REG_4_FFX_RST,
      O => sreg_REG(4)
    );
  sreg_REG_4_FFX_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_4_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_4_FFX_RST
    );
  sreg_REG_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_6_DYMUX,
      CE => VCC,
      CLK => sreg_REG_6_CLKINV,
      SET => GND,
      RST => sreg_REG_6_FFY_RST,
      O => sreg_REG(5)
    );
  sreg_REG_6_FFY_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_6_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_6_FFY_RST
    );
  sreg_REG_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_6_DXMUX,
      CE => VCC,
      CLK => sreg_REG_6_CLKINV,
      SET => GND,
      RST => sreg_REG_6_FFX_RST,
      O => sreg_REG(6)
    );
  sreg_REG_6_FFX_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_6_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_6_FFX_RST
    );
  sreg_REG_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => sreg_REG_8_DYMUX,
      CE => VCC,
      CLK => sreg_REG_8_CLKINV,
      SET => GND,
      RST => sreg_REG_8_FFY_RST,
      O => sreg_REG(7)
    );
  sreg_REG_8_FFY_RSTOR : X_OR2
    port map (
      I0 => sreg_REG_8_SRFFMUX,
      I1 => GSR,
      O => sreg_REG_8_FFY_RST
    );
  D_5_OUTPUT_OTCLK1INV_45 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_5_OUTPUT_OTCLK1INV
    );
  SDATA_IFF_IFF1_RSTOR : X_OR2
    port map (
      I0 => SDATA_IFF_ISR_USED,
      I1 => GSR,
      O => SDATA_IFF_IFF1_RST
    );
  sreg_REG_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => SDATA_IFF_IFFDMUX,
      CE => VCC,
      CLK => SDATA_IFF_ICLK1INV,
      SET => GND,
      RST => SDATA_IFF_IFF1_RST,
      O => sreg_REG(0)
    );
  SDATA_IFF_IFFDMUX_46 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SDATA_INBUF,
      O => SDATA_IFF_IFFDMUX
    );
  SDATA_IFF_ISR_USED_47 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => SDATA_IFF_ISR_USED
    );
  SDATA_IFF_ICLK1INV_48 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => SDATA_IFF_ICLK1INV
    );
  D_5_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q(5),
      O => D_5_O
    );
  D_5_OUTPUT_OFF_O1INV_49 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(5),
      O => D_5_OUTPUT_OFF_O1INV
    );
  reg_Q_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => D_5_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => D_5_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => D_5_OUTPUT_OFF_OFF1_RST,
      O => reg_Q(5)
    );
  D_5_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => D_5_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => D_5_OUTPUT_OFF_OFF1_RST
    );
  D_5_OUTPUT_OFF_OFF1_RSTAND_50 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => D_5_OUTPUT_OFF_OFF1_RSTAND
    );
  D_6_OUTPUT_OTCLK1INV_51 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_6_OUTPUT_OTCLK1INV
    );
  REG_OUT_4_OUTPUT_OTCLK1INV_52 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_4_OUTPUT_OTCLK1INV
    );
  REG_OUT_4_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_4_1,
      O => REG_OUT_4_O
    );
  REG_OUT_4_OUTPUT_OFF_O1INV_53 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(4),
      O => REG_OUT_4_OUTPUT_OFF_O1INV
    );
  reg_Q_4_1_54 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_4_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_4_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_4_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_4_1
    );
  REG_OUT_4_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_4_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_4_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_4_OUTPUT_OFF_OFF1_RSTAND_55 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_4_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_5_OUTPUT_OTCLK1INV_56 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_5_OUTPUT_OTCLK1INV
    );
  REG_OUT_5_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_5_1,
      O => REG_OUT_5_O
    );
  REG_OUT_5_OUTPUT_OFF_O1INV_57 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(5),
      O => REG_OUT_5_OUTPUT_OFF_O1INV
    );
  reg_Q_5_1_58 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_5_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_5_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_5_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_5_1
    );
  REG_OUT_5_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_5_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_5_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_5_OUTPUT_OFF_OFF1_RSTAND_59 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_5_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_1_OUTPUT_OTCLK1INV_60 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_1_OUTPUT_OTCLK1INV
    );
  REG_OUT_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_1_1,
      O => REG_OUT_1_O
    );
  REG_OUT_1_OUTPUT_OFF_O1INV_61 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(1),
      O => REG_OUT_1_OUTPUT_OFF_O1INV
    );
  reg_Q_1_1_62 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => REG_OUT_1_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => REG_OUT_1_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => REG_OUT_1_OUTPUT_OFF_OFF1_RST,
      O => reg_Q_1_1
    );
  REG_OUT_1_OUTPUT_OFF_OFF1_RSTOR : X_OR2
    port map (
      I0 => REG_OUT_1_OUTPUT_OFF_OFF1_RSTAND,
      I1 => GSR,
      O => REG_OUT_1_OUTPUT_OFF_OFF1_RST
    );
  REG_OUT_1_OUTPUT_OFF_OFF1_RSTAND_63 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG_0_N62,
      O => REG_OUT_1_OUTPUT_OFF_OFF1_RSTAND
    );
  REG_OUT_2_OUTPUT_OTCLK1INV_64 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => REG_OUT_2_OUTPUT_OTCLK1INV
    );
  REG_OUT_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => reg_Q_2_1,
      O => REG_OUT_2_O
    );
  REG_OUT_2_OUTPUT_OFF_O1INV_65 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(2),
      O => REG_OUT_2_OUTPUT_OFF_O1INV
    );
  reg_Q_2_1_66 : X_FF
    generic map(
      INIT => '0'