project_timesim.vhd

VHDL source code for test machine.

-- Xilinx Vhdl netlist produced by netgen application (version G.38)
-- Command       : -intstyle ise -s 5 -pcf project.pcf -ngm project.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim project.ncd project_timesim.vhd 
-- Input file    : project.ncd
-- Output file   : project_timesim.vhd
-- Design name   : project
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2v40fg256-5 (PRODUCTION 1.120 2004-11-02, STEPPING 1)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity project is
  port (
    IRQ : out STD_LOGIC; 
    SCLK : in STD_LOGIC := 'X'; 
    SDATA : in STD_LOGIC := 'X'; 
    WR : in STD_LOGIC := 'X'; 
    RD : in STD_LOGIC := 'X'; 
    RESET : in STD_LOGIC := 'X'; 
    D : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    REG_OUT : inout STD_LOGIC_VECTOR ( 7 downto 0 ); 
    A : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end project;

architecture Structure of project is
  signal A_0_IBUF : STD_LOGIC; 
  signal A_1_IBUF : STD_LOGIC; 
  signal RD_IBUF : STD_LOGIC; 
  signal sreg_REG_0_N62 : STD_LOGIC; 
  signal OR2_OUT : STD_LOGIC; 
  signal SCLK_BUFGP : STD_LOGIC; 
  signal SCLK_BUFGP_IBUFG : STD_LOGIC; 
  signal WR_IBUF : STD_LOGIC; 
  signal RESET_IBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal A_0_INBUF : STD_LOGIC; 
  signal A_1_INBUF : STD_LOGIC; 
  signal RD_INBUF : STD_LOGIC; 
  signal IRQ_ENABLE : STD_LOGIC; 
  signal IRQ_GTS_OR_T : STD_LOGIC; 
  signal IRQ_O : STD_LOGIC; 
  signal D_0_ENABLE : STD_LOGIC; 
  signal D_0_GTS_OR_T : STD_LOGIC; 
  signal D_0_O : STD_LOGIC; 
  signal D_0_T : STD_LOGIC; 
  signal D_1_ENABLE : STD_LOGIC; 
  signal D_1_GTS_OR_T : STD_LOGIC; 
  signal D_1_O : STD_LOGIC; 
  signal D_1_T : STD_LOGIC; 
  signal D_2_ENABLE : STD_LOGIC; 
  signal D_2_GTS_OR_T : STD_LOGIC; 
  signal D_2_O : STD_LOGIC; 
  signal D_2_T : STD_LOGIC; 
  signal D_3_ENABLE : STD_LOGIC; 
  signal D_3_GTS_OR_T : STD_LOGIC; 
  signal D_3_O : STD_LOGIC; 
  signal D_3_T : STD_LOGIC; 
  signal D_4_ENABLE : STD_LOGIC; 
  signal D_4_GTS_OR_T : STD_LOGIC; 
  signal D_4_O : STD_LOGIC; 
  signal D_4_T : STD_LOGIC; 
  signal SDATA_INBUF : STD_LOGIC; 
  signal D_5_ENABLE : STD_LOGIC; 
  signal D_5_GTS_OR_T : STD_LOGIC; 
  signal D_5_O : STD_LOGIC; 
  signal D_5_T : STD_LOGIC; 
  signal D_6_ENABLE : STD_LOGIC; 
  signal D_6_GTS_OR_T : STD_LOGIC; 
  signal D_6_O : STD_LOGIC; 
  signal D_6_T : STD_LOGIC; 
  signal D_7_ENABLE : STD_LOGIC; 
  signal D_7_GTS_OR_T : STD_LOGIC; 
  signal D_7_O : STD_LOGIC; 
  signal D_7_T : STD_LOGIC; 
  signal SCLK_INBUF : STD_LOGIC; 
  signal WR_INBUF : STD_LOGIC; 
  signal REG_OUT_0_ENABLE : STD_LOGIC; 
  signal REG_OUT_0_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_0_O : STD_LOGIC; 
  signal REG_OUT_1_ENABLE : STD_LOGIC; 
  signal REG_OUT_1_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_1_O : STD_LOGIC; 
  signal REG_OUT_2_ENABLE : STD_LOGIC; 
  signal REG_OUT_2_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_2_O : STD_LOGIC; 
  signal REG_OUT_3_ENABLE : STD_LOGIC; 
  signal REG_OUT_3_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_3_O : STD_LOGIC; 
  signal REG_OUT_4_ENABLE : STD_LOGIC; 
  signal REG_OUT_4_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_4_O : STD_LOGIC; 
  signal REG_OUT_5_ENABLE : STD_LOGIC; 
  signal REG_OUT_5_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_5_O : STD_LOGIC; 
  signal D_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal RESET_INBUF : STD_LOGIC; 
  signal REG_OUT_6_ENABLE : STD_LOGIC; 
  signal REG_OUT_6_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_6_O : STD_LOGIC; 
  signal REG_OUT_7_ENABLE : STD_LOGIC; 
  signal REG_OUT_7_GTS_OR_T : STD_LOGIC; 
  signal REG_OUT_7_O : STD_LOGIC; 
  signal SCLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal sreg_REG_0_N62_F : STD_LOGIC; 
  signal sreg_REG_0_N62_G : STD_LOGIC; 
  signal sreg_REG_2_DXMUX : STD_LOGIC; 
  signal sreg_REG_2_DYMUX : STD_LOGIC; 
  signal sreg_REG_2_SRFFMUX : STD_LOGIC; 
  signal sreg_REG_2_CLKINV : STD_LOGIC; 
  signal sreg_REG_4_DXMUX : STD_LOGIC; 
  signal sreg_REG_4_DYMUX : STD_LOGIC; 
  signal sreg_REG_4_SRFFMUX : STD_LOGIC; 
  signal sreg_REG_4_CLKINV : STD_LOGIC; 
  signal sreg_REG_6_DXMUX : STD_LOGIC; 
  signal sreg_REG_6_DYMUX : STD_LOGIC; 
  signal sreg_REG_6_SRFFMUX : STD_LOGIC; 
  signal sreg_REG_6_CLKINV : STD_LOGIC; 
  signal D_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal sreg_REG_8_DXMUX : STD_LOGIC; 
  signal sreg_REG_8_DYMUX : STD_LOGIC; 
  signal sreg_REG_8_SRFFMUX : STD_LOGIC; 
  signal sreg_REG_8_CLKINV : STD_LOGIC; 
  signal D_0_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_0_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal D_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_1_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal sreg_REG_2_FFY_RST : STD_LOGIC; 
  signal sreg_REG_2_FFX_RST : STD_LOGIC; 
  signal sreg_REG_4_FFY_RST : STD_LOGIC; 
  signal sreg_REG_4_FFX_RST : STD_LOGIC; 
  signal sreg_REG_6_FFY_RST : STD_LOGIC; 
  signal sreg_REG_6_FFX_RST : STD_LOGIC; 
  signal sreg_REG_8_FFY_RST : STD_LOGIC; 
  signal D_5_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal SDATA_IFF_IFF1_RST : STD_LOGIC; 
  signal SDATA_IFF_ISR_USED : STD_LOGIC; 
  signal SDATA_IFF_ICLK1INV : STD_LOGIC; 
  signal SDATA_IFF_IFFDMUX : STD_LOGIC; 
  signal D_5_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_5_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_5_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_6_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal REG_OUT_4_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_4_1 : STD_LOGIC; 
  signal REG_OUT_4_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_4_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_4_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_5_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_5_1 : STD_LOGIC; 
  signal REG_OUT_5_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_5_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_5_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_1_1 : STD_LOGIC; 
  signal REG_OUT_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_1_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_2_1 : STD_LOGIC; 
  signal REG_OUT_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_2_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_2_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_3_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_3_1 : STD_LOGIC; 
  signal REG_OUT_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_3_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_3_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal D_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_2_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_2_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_3_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal D_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_4_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_4_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_4_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal D_4_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal D_3_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_3_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_6_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_6_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_6_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal D_7_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal D_7_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal D_7_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal D_7_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_0_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_0_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal reg_Q_0_1 : STD_LOGIC; 
  signal REG_OUT_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal REG_OUT_6_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_6_1 : STD_LOGIC; 
  signal REG_OUT_6_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_6_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_6_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal REG_OUT_7_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal reg_Q_7_1 : STD_LOGIC; 
  signal REG_OUT_7_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal REG_OUT_7_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal REG_OUT_7_OUTPUT_OFF_OFF1_RSTAND : STD_LOGIC; 
  signal sreg_REG_8_FFX_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal sreg_REG : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal reg_Q : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  A_0_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A(0),
      O => A_0_INBUF
    );
  A_1_IBUF_1 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A(1),
      O => A_1_INBUF
    );
  RD_IBUF_2 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RD,
      O => RD_INBUF
    );
  IRQ_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => IRQ_O,
      CTL => IRQ_ENABLE,
      O => IRQ
    );
  IRQ_ENABLEINV : X_INV
    port map (
      I => IRQ_GTS_OR_T,
      O => IRQ_ENABLE
    );
  IRQ_GTS_OR_T_3 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => IRQ_GTS_OR_T
    );
  D_0_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_0_O,
      CTL => D_0_ENABLE,
      O => D(0)
    );
  D_0_ENABLEINV : X_INV
    port map (
      I => D_0_GTS_OR_T,
      O => D_0_ENABLE
    );
  D_0_GTS_OR_T_4 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_0_T,
      O => D_0_GTS_OR_T
    );
  D_1_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_1_O,
      CTL => D_1_ENABLE,
      O => D(1)
    );
  D_1_ENABLEINV : X_INV
    port map (
      I => D_1_GTS_OR_T,
      O => D_1_ENABLE
    );
  D_1_GTS_OR_T_5 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_1_T,
      O => D_1_GTS_OR_T
    );
  D_2_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_2_O,
      CTL => D_2_ENABLE,
      O => D(2)
    );
  D_2_ENABLEINV : X_INV
    port map (
      I => D_2_GTS_OR_T,
      O => D_2_ENABLE
    );
  D_2_GTS_OR_T_6 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_2_T,
      O => D_2_GTS_OR_T
    );
  D_3_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_3_O,
      CTL => D_3_ENABLE,
      O => D(3)
    );
  D_3_ENABLEINV : X_INV
    port map (
      I => D_3_GTS_OR_T,
      O => D_3_ENABLE
    );
  D_3_GTS_OR_T_7 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_3_T,
      O => D_3_GTS_OR_T
    );
  D_4_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_4_O,
      CTL => D_4_ENABLE,
      O => D(4)
    );
  D_4_ENABLEINV : X_INV
    port map (
      I => D_4_GTS_OR_T,
      O => D_4_ENABLE
    );
  D_4_GTS_OR_T_8 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_4_T,
      O => D_4_GTS_OR_T
    );
  SDATA_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SDATA,
      O => SDATA_INBUF
    );
  D_5_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_5_O,
      CTL => D_5_ENABLE,
      O => D(5)
    );
  D_5_ENABLEINV : X_INV
    port map (
      I => D_5_GTS_OR_T,
      O => D_5_ENABLE
    );
  D_5_GTS_OR_T_9 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_5_T,
      O => D_5_GTS_OR_T
    );
  D_6_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_6_O,
      CTL => D_6_ENABLE,
      O => D(6)
    );
  D_6_ENABLEINV : X_INV
    port map (
      I => D_6_GTS_OR_T,
      O => D_6_ENABLE
    );
  D_6_GTS_OR_T_10 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_6_T,
      O => D_6_GTS_OR_T
    );
  D_7_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_7_O,
      CTL => D_7_ENABLE,
      O => D(7)
    );
  D_7_ENABLEINV : X_INV
    port map (
      I => D_7_GTS_OR_T,
      O => D_7_ENABLE
    );
  D_7_GTS_OR_T_11 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_7_T,
      O => D_7_GTS_OR_T
    );
  SCLK_BUFGP_IBUFG_12 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK,
      O => SCLK_INBUF
    );
  WR_IBUF_13 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => WR,
      O => WR_INBUF
    );
  REG_OUT_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_0_O,
      CTL => REG_OUT_0_ENABLE,
      O => REG_OUT(0)
    );
  REG_OUT_0_ENABLEINV : X_INV
    port map (
      I => REG_OUT_0_GTS_OR_T,
      O => REG_OUT_0_ENABLE
    );
  REG_OUT_0_GTS_OR_T_14 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_0_GTS_OR_T
    );
  REG_OUT_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_1_O,
      CTL => REG_OUT_1_ENABLE,
      O => REG_OUT(1)
    );
  REG_OUT_1_ENABLEINV : X_INV
    port map (
      I => REG_OUT_1_GTS_OR_T,
      O => REG_OUT_1_ENABLE
    );
  REG_OUT_1_GTS_OR_T_15 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_1_GTS_OR_T
    );
  REG_OUT_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_2_O,
      CTL => REG_OUT_2_ENABLE,
      O => REG_OUT(2)
    );
  REG_OUT_2_ENABLEINV : X_INV
    port map (
      I => REG_OUT_2_GTS_OR_T,
      O => REG_OUT_2_ENABLE
    );
  REG_OUT_2_GTS_OR_T_16 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_2_GTS_OR_T
    );
  REG_OUT_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_3_O,
      CTL => REG_OUT_3_ENABLE,
      O => REG_OUT(3)
    );
  REG_OUT_3_ENABLEINV : X_INV
    port map (
      I => REG_OUT_3_GTS_OR_T,
      O => REG_OUT_3_ENABLE
    );
  REG_OUT_3_GTS_OR_T_17 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_3_GTS_OR_T
    );
  REG_OUT_4_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_4_O,
      CTL => REG_OUT_4_ENABLE,
      O => REG_OUT(4)
    );
  REG_OUT_4_ENABLEINV : X_INV
    port map (
      I => REG_OUT_4_GTS_OR_T,
      O => REG_OUT_4_ENABLE
    );
  REG_OUT_4_GTS_OR_T_18 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_4_GTS_OR_T
    );
  REG_OUT_5_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_5_O,
      CTL => REG_OUT_5_ENABLE,
      O => REG_OUT(5)
    );
  REG_OUT_5_ENABLEINV : X_INV
    port map (
      I => REG_OUT_5_GTS_OR_T,
      O => REG_OUT_5_ENABLE
    );
  REG_OUT_5_GTS_OR_T_19 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_5_GTS_OR_T
    );
  D_0_OUTPUT_OTCLK1INV_20 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => sreg_REG(8),
      O => D_0_OUTPUT_OTCLK1INV
    );
  RESET_IBUF_21 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET,
      O => RESET_INBUF
    );
  REG_OUT_6_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_6_O,
      CTL => REG_OUT_6_ENABLE,
      O => REG_OUT(6)
    );
  REG_OUT_6_ENABLEINV : X_INV
    port map (
      I => REG_OUT_6_GTS_OR_T,
      O => REG_OUT_6_ENABLE
    );
  REG_OUT_6_GTS_OR_T_22 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_6_GTS_OR_T
    );
  REG_OUT_7_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => REG_OUT_7_O,
      CTL => REG_OUT_7_ENABLE,
      O => REG_OUT(7)
    );
  REG_OUT_7_ENABLEINV : X_INV
    port map (
      I => REG_OUT_7_GTS_OR_T,
      O => REG_OUT_7_ENABLE
    );
  REG_OUT_7_GTS_OR_T_23 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => REG_OUT_7_GTS_OR_T
    );
  SCLK_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => SCLK_BUFGP_IBUFG,
      I1 => GND,