indicator.syr

VHDL source code for test machine.

Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: indicator.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : indicator.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : indicator
Output Format                      : NGC
Target Device                      : xc2v40-5-fg256

---- Source Options
Top Module Name                    : indicator
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : indicator.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd in Library work.
Architecture behavioral of Entity indicator is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <indicator> (Architecture <behavioral>).
WARNING:Xst:819 - D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd line 25: The following signals are missing in the process sensitivity list:
   Q.
Entity <indicator> analyzed. Unit <indicator> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <indicator>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd.
    Found 23-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <indicator> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 23-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <indicator> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block indicator, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : indicator.ngr
Top Level Output File Name         : indicator
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 4

Macro Statistics :
# Registers                        : 1
#      23-bit register             : 1
# Adders/Subtractors               : 1
#      23-bit adder                : 1

Cell Usage :
# BELS                             : 70
#      GND                         : 1
#      LUT1                        : 2
#      LUT1_D                      : 1
#      LUT1_L                      : 21
#      MUXCY                       : 22
#      VCC                         : 1
#      XORCY                       : 22
# FlipFlops/Latches                : 23
#      FDC                         : 23
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 3
#      IBUF                        : 1
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      13  out of    256     5%  
 Number of Slice Flip Flops:            23  out of    512     4%  
 Number of 4 input LUTs:                24  out of    512     4%  
 Number of bonded IOBs:                  3  out of     88     3%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK_IN                             | BUFGP                  | 23    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.980ns (Maximum Frequency: 251.256MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.852ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK_IN'
Delay:               3.980ns (Levels of Logic = 24)
  Source:            Q_0 (FF)
  Destination:       Q_22 (FF)
  Source Clock:      CLK_IN rising
  Destination Clock: CLK_IN rising

  Data Path: Q_0 to Q_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.494   0.450  Q_0 (Q_0)
     LUT1_D:I0->LO         1   0.382   0.000  Q_LPM_COUNTER_1__n0000<0>lut (N459)
     MUXCY:S->O            1   0.259   0.000  Q_LPM_COUNTER_1__n0000<0>cy (Q_LPM_COUNTER_1__n0000<0>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<1>cy (Q_LPM_COUNTER_1__n0000<1>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<2>cy (Q_LPM_COUNTER_1__n0000<2>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<3>cy (Q_LPM_COUNTER_1__n0000<3>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<4>cy (Q_LPM_COUNTER_1__n0000<4>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<5>cy (Q_LPM_COUNTER_1__n0000<5>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<6>cy (Q_LPM_COUNTER_1__n0000<6>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<7>cy (Q_LPM_COUNTER_1__n0000<7>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<8>cy (Q_LPM_COUNTER_1__n0000<8>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<9>cy (Q_LPM_COUNTER_1__n0000<9>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<10>cy (Q_LPM_COUNTER_1__n0000<10>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<11>cy (Q_LPM_COUNTER_1__n0000<11>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<12>cy (Q_LPM_COUNTER_1__n0000<12>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<13>cy (Q_LPM_COUNTER_1__n0000<13>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<14>cy (Q_LPM_COUNTER_1__n0000<14>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<15>cy (Q_LPM_COUNTER_1__n0000<15>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<16>cy (Q_LPM_COUNTER_1__n0000<16>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<17>cy (Q_LPM_COUNTER_1__n0000<17>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<18>cy (Q_LPM_COUNTER_1__n0000<18>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<19>cy (Q_LPM_COUNTER_1__n0000<19>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Q_LPM_COUNTER_1__n0000<20>cy (Q_LPM_COUNTER_1__n0000<20>_cyo)
     MUXCY:CI->O           0   0.046   0.000  Q_LPM_COUNTER_1__n0000<21>cy (Q_LPM_COUNTER_1__n0000<21>_cyo)
     XORCY:CI->O           1   1.107   0.000  Q_LPM_COUNTER_1__n0000<22>_xor (Q__n0000<22>)
     FDC:D                     0.322          Q_22
    ----------------------------------------
    Total                      3.980ns (3.530ns logic, 0.450ns route)
                                       (88.7% logic, 11.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_IN'
Offset:              5.852ns (Levels of Logic = 2)
  Source:            Q_22 (FF)
  Destination:       nIndy (PAD)
  Source Clock:      CLK_IN rising

  Data Path: Q_22 to nIndy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.494   0.630  Q_22 (Q_22)
     LUT1:I0->O            1   0.382   0.450  nIndy1 (nIndy_OBUF)
     OBUF:I->O                 3.896          nIndy_OBUF (nIndy)
    ----------------------------------------
    Total                      5.852ns (4.772ns logic, 1.080ns route)
                                       (81.5% logic, 18.5% route)

=========================================================================
CPU : 13.06 / 14.50 s | Elapsed : 13.00 / 14.00 s
 
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Total memory usage is 62092 kilobytes