sreg8.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.ALL;
--use project.vhdl;
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--signal : SDATA : in std_logic;
entity sreg8 is

	port (DIN	: in std_logic;
	      Q		: out std_logic_vector (8 downto 0);
		 	CLK	: in std_logic;		 		
			CLR	: in std_logic
	 );

end sreg8;

architecture Behavioral of sreg8 is

signal REG: STD_LOGIC_VECTOR(8 downto 0); 
begin
	process (CLK)
		begin
   		  if (CLR='0') then 							--Asinhronen nulirasht vhod
					REG <= "000000000";
			  elsif ( CLK'event and CLK='1') then	--CLR='0' i CLK='1' 
					REG <= REG(7 downto 0) & DIN;		
			  end if;
				Q <= REG;
	end process;
end Behavioral;
 

 -----------------------------------------------------
-- 

-- 	if CLK'event and CLK='1' then
--				if (CLR='1') then
-- 					REG <= "000000000";
--				else
-- 					REG <= REG(7 downto 0) & DIN;
--				end if;
--   		end if;
--			Q <= REG;