count_4.vhf

vhdl source vhdl source vhdl source vhdl source vhdl source vhdl source vhdl source vhdl source vhd

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : count_4.vhf
-- /___/   /\     Timestamp : 02/16/2008 12:54:08
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx91i\bin\nt\sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w C:/Xilinx91i/ISEexamples/count_4/count_4.sch count_4.vhf
--Design Name: count_4
--Device: xc9500
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity CD4CE_MXILINX_count_4 is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          CEO : out   std_logic; 
          Q0  : out   std_logic; 
          Q1  : out   std_logic; 
          Q2  : out   std_logic; 
          Q3  : out   std_logic; 
          TC  : out   std_logic);
end CD4CE_MXILINX_count_4;

architecture BEHAVIORAL of CD4CE_MXILINX_count_4 is
   attribute BOX_TYPE   : string ;
   signal AO3A     : std_logic;
   signal AX1      : std_logic;
   signal AX2      : std_logic;
   signal A03B     : std_logic;
   signal D0       : std_logic;
   signal D1       : std_logic;
   signal D2       : std_logic;
   signal D3       : std_logic;
   signal OX3      : std_logic;
   signal Q0_DUMMY : std_logic;
   signal Q1_DUMMY : std_logic;
   signal Q2_DUMMY : std_logic;
   signal Q3_DUMMY : std_logic;
   signal TC_DUMMY : std_logic;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component XOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component AND4B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
   
   component FDCE
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q0 <= Q0_DUMMY;
   Q1 <= Q1_DUMMY;
   Q2 <= Q2_DUMMY;
   Q3 <= Q3_DUMMY;
   TC <= TC_DUMMY;
   I_36_70 : AND3
      port map (I0=>Q2_DUMMY,
                I1=>Q0_DUMMY,
                I2=>Q1_DUMMY,
                O=>A03B);
   
   I_36_73 : XOR2
      port map (I0=>Q3_DUMMY,
                I1=>OX3,
                O=>D3);
   
   I_36_75 : OR2
      port map (I0=>AO3A,
                I1=>A03B,
                O=>OX3);
   
   I_36_77 : AND2
      port map (I0=>Q0_DUMMY,
                I1=>Q1_DUMMY,
                O=>AX2);
   
   I_36_78 : XOR2
      port map (I0=>Q2_DUMMY,
                I1=>AX2,
                O=>D2);
   
   I_36_81 : AND2B1
      port map (I0=>Q3_DUMMY,
                I1=>Q0_DUMMY,
                O=>AX1);
   
   I_36_83 : INV
      port map (I=>Q0_DUMMY,
                O=>D0);
   
   I_36_86 : XOR2
      port map (I0=>Q1_DUMMY,
                I1=>AX1,
                O=>D1);
   
   I_36_88 : AND2
      port map (I0=>Q3_DUMMY,
                I1=>Q0_DUMMY,
                O=>AO3A);
   
   I_36_99 : AND2
      port map (I0=>CE,
                I1=>TC_DUMMY,
                O=>CEO);
   
   I_36_105 : AND4B2
      port map (I0=>Q2_DUMMY,
                I1=>Q1_DUMMY,
                I2=>Q0_DUMMY,
                I3=>Q3_DUMMY,
                O=>TC_DUMMY);
   
   U0 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D0,
                Q=>Q0_DUMMY);
   
   U1 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D1,
                Q=>Q1_DUMMY);
   
   U2 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D2,
                Q=>Q2_DUMMY);
   
   U3 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D3,
                Q=>Q3_DUMMY);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity count_4 is
   port ( );
end count_4;

architecture BEHAVIORAL of count_4 is
   attribute HU_SET     : string ;
   signal XLXI_1_C_openSignal   : std_logic;
   signal XLXI_1_CE_openSignal  : std_logic;
   signal XLXI_1_CLR_openSignal : std_logic;
   component CD4CE_MXILINX_count_4
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             CEO : out   std_logic; 
             Q0  : out   std_logic; 
             Q1  : out   std_logic; 
             Q2  : out   std_logic; 
             Q3  : out   std_logic; 
             TC  : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_1 : label is "XLXI_1_0";
begin
   XLXI_1 : CD4CE_MXILINX_count_4
      port map (C=>XLXI_1_C_openSignal,
                CE=>XLXI_1_CE_openSignal,
                CLR=>XLXI_1_CLR_openSignal,
                CEO=>open,
                Q0=>open,
                Q1=>open,
                Q2=>open,
                Q3=>open,
                TC=>open);
   
end BEHAVIORAL;