hbwdcf0428.v

11阶滤波器的verilog基本代码描述

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:56:03 04/10/2009 
// Design Name: 
// Module Name:    HBWDCF 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module HBWDCF(
      Sysclk_h,
		Grst_n,
		ddcen_h,
		ddcrdy_h,   
		ddcwrdy_h,
		hbwdcfdin,
		hbwdcfdout
		);
		input Sysclk_h,
				Grst_n,
				ddcrdy_h,
				ddcen_h;
		input ddcwrdy_h;
		
		input  [15:0] hbwdcfdin;
		output [15:0] hbwdcfdout;
		
/*********************************************************************************/
//control	
		wire contr_rw;		
		assign contr_rw=ddcwrdy_h;
		wire ddcwdcfen_h;
		assign ddcwdcfen_h=ddcen_h&ddcrdy_h;
/*****************************************************************************/
     //demux
//for channel 0
	reg [15:0] dinch0_w;
	
	always@(posedge Sysclk_h)
			case (contr_rw) 
			1'b0: dinch0_w<=hbwdcfdin;
			1'b1: dinch0_w<=16'h0000;
			default: dinch0_w<=16'h0000;
			endcase
//	assign dinch0_w=contr_rw?16'h0000:hbwdcfdin;
	
	reg [15:0] dmch0_wr0,dmch0_wr1;
	wire [15:0] dmch0_w0,dmch0_w1;
	
	assign dmch0_w0=contr_rw?dmch0_wr0:dinch0_w;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dmch0_wr0<=0;
				end
			else if (ddcwdcfen_h) begin
//			else if  (ddcen_h) begin
					dmch0_wr0<=dmch0_w0;
					end
				
	assign dmch0_w1=contr_rw?dmch0_wr1:dmch0_wr0;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dmch0_wr1<=0;
				end
			else if (ddcwdcfen_h) begin
					dmch0_wr1<=dmch0_w1;
					end
				
// for channel 1
//	reg [15:0] dinch1_r;
	reg [15:0] dinch1_w;
	
	always@(posedge Sysclk_h)
			case (contr_rw) 
			1'b0:dinch1_w<=16'h0000;
			1'b1:dinch1_w<=hbwdcfdin;
			default:dinch1_w<=16'h0000;
			endcase
			
//	assign dinch1_w=contr_rw?hbwdcfdin:16'h0000;
	
	reg [15:0] dmch1_wr0,dmch1_wr1;
	wire [15:0] dmch1_w0,dmch1_w1;
	
	assign dmch1_w0=contr_rw?dinch1_w:dmch1_wr0;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dmch1_wr0<=0;
				end
			else if (ddcwdcfen_h) begin
//			else if  (ddcen_h) begin
					dmch1_wr0<=dmch1_w0;
					end
				
	assign dmch1_w1=contr_rw?dmch1_wr1:dmch1_wr0;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dmch1_wr1<=0;
				end
			else if (ddcwdcfen_h) begin
					dmch1_wr1<=dmch1_w1;
					end
/*********************************************************************************************/
/*****************************wave pipelining filter******************************************/
//time sharing of coef0, coef1,coef2,coef3
	wire [1:0] coefthctr_w;
	
	assign coefthctr_w[0]=ddcrdy_h;
	assign coefthctr_w[1]=contr_rw;
	
	wire [21:0] wpthsg0_r;
	assign wpthsg0_r={dmch0_wr1,5'b00000}-{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
									  dmch0_wr1};//31x
		
	reg [27:0] wpthsg1_r; 
	
	always@(coefthctr_w, wpthsg0_r,dmch0_wr1)
		case (coefthctr_w)
			2'b00: wpthsg1_r={wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r}
			                 +{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
								  dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1,2'b00};//35x
			2'b01: wpthsg1_r={wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r}
			                 +{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
								  dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1,2'b00};//35x
			2'b10: wpthsg1_r={dmch0_wr1,11'b000_0000_0000}-{wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],
								  wpthsg0_r};//2017x
			2'b11: wpthsg1_r={dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1,9'b0_0000_0000}+{wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r[21],wpthsg0_r};//543x
		endcase
		
		
reg [27:0] wpthsg2_r;
	
	always@(coefthctr_w, wpthsg1_r,dmch0_wr1)
		case (coefthctr_w)
			2'b00: wpthsg2_r=wpthsg1_r;//35x
			2'b01: wpthsg2_r={dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
			       dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1,4'b0000}-{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
					 dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1};//15x
			2'b10: wpthsg2_r=wpthsg1_r;//2017x
			2'b11: wpthsg2_r={dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
			       dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1,4'b0000}-{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
					 dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1};//15x
		endcase

wire [33:0] wpthsg1lcef_w;
	
	assign wpthsg1lcef_w={wpthsg2_r,5'b00000}-{dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
								dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],
								dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1[15],dmch0_wr1};	//479x	

	reg [38:0] wpthsg3_r;
	
	always@(coefthctr_w, wpthsg1_r,wpthsg2_r,wpthsg1lcef_w)
		case (coefthctr_w)
			2'b00: wpthsg3_r={wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],
			                  wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r};//35x
			2'b01: wpthsg3_r={wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r,5'b00000}
			                  -{wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],
									wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r,1'b0};//410x
			2'b10: wpthsg3_r={wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],
			                  wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r[27],wpthsg2_r};//2017x
			2'b11: wpthsg3_r={wpthsg1lcef_w,4'b0000}+{wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],
			                 wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r[27],wpthsg1_r,2'b00};//9836x
		endcase

//folding model
	wire [15:0] fm0mul_w;
	
	assign fm0mul_w=wpthsg3_r;
	
   reg [15:0] fm0add_r;
	reg [15:0] fm0_r0,fm0_r1,fm0_r2,fm0_r3,fm0_r4,fm0_r5,fm0_r6,fm0_r7,fm0_r8;

	always@(coefthctr_w, fm0mul_w,fm0_r4,fm0_r8)
		case (coefthctr_w)
			2'b00: fm0add_r=fm0mul_w;
			2'b01: fm0add_r=fm0mul_w+fm0_r8;
			2'b10: fm0add_r=fm0mul_w+fm0_r8;
			2'b11: fm0add_r=fm0_r4;  //修改：2'b11: fm0add_r=fm0mul_w+fm0_r8;
	   endcase
		
	wire [15:0] fm0add_rw;
	
	assign fm0add_rw=fm0add_r;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if(Grst_n==1'b0) begin
			fm0_r0<=0;
			fm0_r1<=0;
			fm0_r2<=0;
			fm0_r3<=0;
			fm0_r4<=0;
			fm0_r5<=0;
			fm0_r6<=0;
			fm0_r7<=0;
			fm0_r8<=0;
			end
		else if (ddcen_h) begin
		      fm0_r8<=fm0_r7;
				fm0_r7<=fm0_r6;
				fm0_r6<=fm0_r5;
				fm0_r5<=fm0_r4;
		      fm0_r4<=fm0_r3;
		      fm0_r3<=fm0_r2;
		      fm0_r2<=fm0_r1;
				fm0_r1<=fm0_r0;
				fm0_r0<=fm0add_rw;
				end
					
	wire [15:0] fm1mul_w;
	
	assign fm1mul_w=dmch1_wr1;
	
	reg [15:0] fm1add_r;
	reg [15:0] fm1_r0,fm1_r1,fm1_r2;
	
   always@(coefthctr_w, fm1mul_w,fm0add_rw)
		case (coefthctr_w)
			2'b00: fm1add_r=fm1mul_w;
			2'b01: fm1add_r=fm1mul_w;
			2'b10: fm1add_r=fm1mul_w;
			2'b11: fm1add_r=fm1mul_w+fm0add_rw;//修改：2'b11: fm1add_r=fm1mul_w+fm0_r3；
	   endcase
	
	wire [15:0] fm1add_rw;
	
	assign fm1add_rw=fm1add_r;
		
	always@(posedge Sysclk_h or negedge Grst_n)
		if(Grst_n==1'b0) begin
		   fm1_r2<=0;
			fm1_r1<=0;
			fm1_r0<=0;
			end
		else if (ddcen_h) begin
		      fm1_r2<=fm1_r1;
				fm1_r1<=fm1_r0;
				fm1_r0<=fm1add_rw;
				end


	wire [15:0] fm2mul_w;
	
	assign fm2mul_w=fm0mul_w;
	
	reg [15:0] fm2add_r;
	reg [15:0] fm2_r0,fm2_r1,fm2_r2,fm2_r3,fm2_r4,fm2_r5,fm2_r6;

	always@(coefthctr_w, fm2mul_w,fm1_r2,fm2_r6)
		case (coefthctr_w)
			2'b00: fm2add_r=fm2mul_w+fm2_r6;
			2'b01: fm2add_r=fm2mul_w+fm2_r6;
			2'b10: fm2add_r=fm2mul_w+fm2_r6;
			2'b11: fm2add_r=fm2mul_w+fm1_r2;//修改：2'b11: fm2add_r=fm2mul_w+fm1_r3;
	   endcase
		
	wire [15:0] fm2add_rw;
	
	assign fm2add_rw=fm2add_r;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if(Grst_n==1'b0) begin
		   fm2_r6<=0;
			fm2_r5<=0;
			fm2_r4<=0;
			fm2_r3<=0;
			fm2_r2<=0;
			fm2_r1<=0;
			fm2_r0<=0;
			end
		else if (ddcen_h) begin
		      fm2_r6<=fm2_r5;
				fm2_r5<=fm2_r4;
				fm2_r4<=fm2_r3;
				fm2_r3<=fm2_r2;
				fm2_r2<=fm2_r1;
				fm2_r1<=fm2_r0;
				fm2_r0<=fm2add_rw;
				end	
//output
   reg [15:0] fmdout_r;
	reg [15:0] fmdout_rwr;
	
	always@(coefthctr_w, fm2add_rw,fmdout_rwr)
		case (coefthctr_w)
			2'b00: fmdout_r=fm2add_rw;
			2'b01: fmdout_r=fmdout_rwr;
			2'b10: fmdout_r=16'h0000;
			2'b11: fmdout_r=16'h0000;
	   endcase
   
	wire [15:0] fmdout_rw;
	
	assign fmdout_rw=fmdout_r;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if(Grst_n==1'b0) begin
			fmdout_rwr<=0;
			end
		else if (ddcen_h) begin
				fmdout_rwr<=fmdout_rw;
				end
				
	reg [15:0] dout_wr0,dout_wr1;
	wire [15:0] dout_w0,dout_w1;
	
	assign dout_w0=contr_rw?dout_wr0:fmdout_rw;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dout_wr0<=0;
				end
			else if (ddcen_h) begin
					dout_wr0<=dout_w0;
					end
				
	assign dout_w1=contr_rw?dout_wr0:dout_wr1;
	
	always@(posedge Sysclk_h or negedge Grst_n)
		if (Grst_n==1'b0) begin
				dout_wr1<=0;
				end
			else if (ddcen_h) begin
					dout_wr1<=dout_w1;
					end	
	
	assign hbwdcfdout=dout_wr1;

endmodule