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📄 step_a.fit.eqn

📁 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写
💻 EQN
📖 第 1 页 / 共 5 页
字号:
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12345 
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[2] = DB1_q_a[15]_PORT_A_data_out[7];

--DB1_q_a[6] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[6] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[6] = DB1_q_a[15]_PORT_A_data_out[6];

--DB1_q_a[10] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[10] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[10] = DB1_q_a[15]_PORT_A_data_out[5];

--DB1_q_a[14] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[14] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[14] = DB1_q_a[15]_PORT_A_data_out[4];

--DB1_q_a[3] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[3] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[3] = DB1_q_a[15]_PORT_A_data_out[3];

--DB1_q_a[7] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[7] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[7] = DB1_q_a[15]_PORT_A_data_out[2];

--DB1_q_a[11] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[11] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[11] = DB1_q_a[15]_PORT_A_data_out[1];

--DB1_q_b[4] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[4] at M4K_X13_Y9
DB1_q_b[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_b[15]_PORT_A_data_in_reg = DFFE(DB1_q_b[15]_PORT_A_data_in, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_b[15]_PORT_B_data_in_reg = DFFE(DB1_q_b[15]_PORT_B_data_in, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[15]_PORT_A_address_reg = DFFE(DB1_q_b[15]_PORT_A_address, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[15]_PORT_B_address_reg = DFFE(DB1_q_b[15]_PORT_B_address, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_write_enable = GND;
DB1_q_b[15]_PORT_A_write_enable_reg = DFFE(DB1_q_b[15]_PORT_A_write_enable, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_write_enable = EB1L2;
DB1_q_b[15]_PORT_B_write_enable_reg = DFFE(DB1_q_b[15]_PORT_B_write_enable, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_clock_0 = GLOBAL(clk0);
DB1_q_b[15]_clock_1 = GLOBAL(A1L5);
DB1_q_b[15]_PORT_B_data_out = MEMORY(DB1_q_b[15]_PORT_A_data_in_reg, DB1_q_b[15]_PORT_B_data_in_reg, DB1_q_b[15]_PORT_A_address_reg, DB1_q_b[15]_PORT_B_address_reg, DB1_q_b[15]_PORT_A_write_enable_reg, DB1_q_b[15]_PORT_B_write_enable_reg, , , DB1_q_b[15]_clock_0, DB1_q_b[15]_clock_1, , , , );
DB1_q_b[4] = DB1_q_b[15]_PORT_B_data_out[15];

--DB1_q_b[8] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[8] at M4K_X13_Y9
DB1_q_b[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_b[15]_PORT_A_data_in_reg = DFFE(DB1_q_b[15]_PORT_A_data_in, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_b[15]_PORT_B_data_in_reg = DFFE(DB1_q_b[15]_PORT_B_data_in, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[15]_PORT_A_address_reg = DFFE(DB1_q_b[15]_PORT_A_address, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[15]_PORT_B_address_reg = DFFE(DB1_q_b[15]_PORT_B_address, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_write_enable = GND;
DB1_q_b[15]_PORT_A_write_enable_reg = DFFE(DB1_q_b[15]_PORT_A_write_enable, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_write_enable = EB1L2;
DB1_q_b[15]_PORT_B_write_enable_reg = DFFE(DB1_q_b[15]_PORT_B_write_enable, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_clock_0 = GLOBAL(clk0);
DB1_q_b[15]_clock_1 = GLOBAL(A1L5);
DB1_q_b[15]_PORT_B_data_out = MEMORY(DB1_q_b[15]_PORT_A_data_in_reg, DB1_q_b[15]_PORT_B_data_in_reg, DB1_q_b[15]_PORT_A_address_reg, DB1_q_b[15]_PORT_B_address_reg, DB1_q_b[15]_PORT_A_write_enable_reg, DB1_q_b[15]_PORT_B_write_enable_reg, , , DB1_q_b[15]_clock_0, DB1_q_b[15]_clock_1, , , , );
DB1_q_b[8] = DB1_q_b[15]_PORT_B_data_out[14];

--DB1_q_b[12] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[12] at M4K_X13_Y9
DB1_q_b[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_b[15]_PORT_A_data_in_reg = DFFE(DB1_q_b[15]_PORT_A_data_in, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_b[15]_PORT_B_data_in_reg = DFFE(DB1_q_b[15]_PORT_B_data_in, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[15]_PORT_A_address_reg = DFFE(DB1_q_b[15]_PORT_A_address, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[15]_PORT_B_address_reg = DFFE(DB1_q_b[15]_PORT_B_address, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_write_enable = GND;
DB1_q_b[15]_PORT_A_write_enable_reg = DFFE(DB1_q_b[15]_PORT_A_write_enable, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_write_enable = EB1L2;
DB1_q_b[15]_PORT_B_write_enable_reg = DFFE(DB1_q_b[15]_PORT_B_write_enable, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_clock_0 = GLOBAL(clk0);
DB1_q_b[15]_clock_1 = GLOBAL(A1L5);
DB1_q_b[15]_PORT_B_data_out = MEMORY(DB1_q_b[15]_PORT_A_data_in_reg, DB1_q_b[15]_PORT_B_data_in_reg, DB1_q_b[15]_PORT_A_address_reg, DB1_q_b[15]_PORT_B_address_reg, DB1_q_b[15]_PORT_A_write_enable_reg, DB1_q_b[15]_PORT_B_write_enable_reg, , , DB1_q_b[15]_clock_0, DB1_q_b[15]_clock_1, , , , );
DB1_q_b[12] = DB1_q_b[15]_PORT_B_data_out[13];

--DB1_q_b[0] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[0] at M4K_X13_Y9
DB1_q_b[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_b[15]_PORT_A_data_in_reg = DFFE(DB1_q_b[15]_PORT_A_data_in, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_b[15]_PORT_B_data_in_reg = DFFE(DB1_q_b[15]_PORT_B_data_in, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[15]_PORT_A_address_reg = DFFE(DB1_q_b[15]_PORT_A_address, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[15]_PORT_B_address_reg = DFFE(DB1_q_b[15]_PORT_B_address, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_write_enable = GND;
DB1_q_b[15]_PORT_A_write_enable_reg = DFFE(DB1_q_b[15]_PORT_A_write_enable, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_write_enable = EB1L2;
DB1_q_b[15]_PORT_B_write_enable_reg = DFFE
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