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📄 step_a.fit.eqn

📁 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写
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U1_lcarry[2]_cout_0 = DB1_q_a[14] & (!U1_lcarry[1] # !D1_CQI[3]) # !DB1_q_a[14] & !D1_CQI[3] & !U1_lcarry[1];
U1_lcarry[2] = CARRY(U1_lcarry[2]_cout_0);

--U1L21 is cmp3:93|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[2]~COUT1_122 at LC_X16_Y10_N2
--operation mode is arithmetic

U1L21_cout_1 = DB1_q_a[14] & (!U1L9 # !D1_CQI[3]) # !DB1_q_a[14] & !D1_CQI[3] & !U1L9;
U1L21 = CARRY(U1L21_cout_1);


--DB1_q_a[15] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[15] at M4K_X13_Y9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 16, Port B Depth: 32, Port B Width: 16
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[15] = DB1_q_a[15]_PORT_A_data_out[0];

--DB1_q_b[15] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[15] at M4K_X13_Y9
DB1_q_b[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_b[15]_PORT_A_data_in_reg = DFFE(DB1_q_b[15]_PORT_A_data_in, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_b[15]_PORT_B_data_in_reg = DFFE(DB1_q_b[15]_PORT_B_data_in, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[15]_PORT_A_address_reg = DFFE(DB1_q_b[15]_PORT_A_address, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[15]_PORT_B_address_reg = DFFE(DB1_q_b[15]_PORT_B_address, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_PORT_A_write_enable = GND;
DB1_q_b[15]_PORT_A_write_enable_reg = DFFE(DB1_q_b[15]_PORT_A_write_enable, DB1_q_b[15]_clock_0, , , );
DB1_q_b[15]_PORT_B_write_enable = EB1L2;
DB1_q_b[15]_PORT_B_write_enable_reg = DFFE(DB1_q_b[15]_PORT_B_write_enable, DB1_q_b[15]_clock_1, , , );
DB1_q_b[15]_clock_0 = GLOBAL(clk0);
DB1_q_b[15]_clock_1 = GLOBAL(A1L5);
DB1_q_b[15]_PORT_B_data_out = MEMORY(DB1_q_b[15]_PORT_A_data_in_reg, DB1_q_b[15]_PORT_B_data_in_reg, DB1_q_b[15]_PORT_A_address_reg, DB1_q_b[15]_PORT_B_address_reg, DB1_q_b[15]_PORT_A_write_enable_reg, DB1_q_b[15]_PORT_B_write_enable_reg, , , DB1_q_b[15]_clock_0, DB1_q_b[15]_clock_1, , , , );
DB1_q_b[15] = DB1_q_b[15]_PORT_B_data_out[0];

--DB1_q_a[4] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[4] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[4] = DB1_q_a[15]_PORT_A_data_out[15];

--DB1_q_a[8] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[8] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[8] = DB1_q_a[15]_PORT_A_data_out[14];

--DB1_q_a[12] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[12] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[12] = DB1_q_a[15]_PORT_A_data_out[13];

--DB1_q_a[0] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[0] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[0] = DB1_q_a[15]_PORT_A_data_out[12];

--DB1_q_a[1] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[1] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[1] = DB1_q_a[15]_PORT_A_data_out[11];

--DB1_q_a[5] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[5] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[5] = DB1_q_a[15]_PORT_A_data_out[10];

--DB1_q_a[9] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[9] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[9] = DB1_q_a[15]_PORT_A_data_out[9];

--DB1_q_a[13] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[13] at M4K_X13_Y9
DB1_q_a[15]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_data_in = BUS(EB1_ram_rom_data_reg[15], EB1_ram_rom_data_reg[11], EB1_ram_rom_data_reg[7], EB1_ram_rom_data_reg[3], EB1_ram_rom_data_reg[14], EB1_ram_rom_data_reg[10], EB1_ram_rom_data_reg[6], EB1_ram_rom_data_reg[2], EB1_ram_rom_data_reg[13], EB1_ram_rom_data_reg[9], EB1_ram_rom_data_reg[5], EB1_ram_rom_data_reg[1], EB1_ram_rom_data_reg[0], EB1_ram_rom_data_reg[12], EB1_ram_rom_data_reg[8], EB1_ram_rom_data_reg[4]);
DB1_q_a[15]_PORT_B_data_in_reg = DFFE(DB1_q_a[15]_PORT_B_data_in, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_PORT_A_write_enable = GND;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_write_enable = EB1L2;
DB1_q_a[15]_PORT_B_write_enable_reg = DFFE(DB1_q_a[15]_PORT_B_write_enable, DB1_q_a[15]_clock_1, , , );
DB1_q_a[15]_clock_0 = GLOBAL(clk0);
DB1_q_a[15]_clock_1 = GLOBAL(A1L5);
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, DB1_q_a[15]_PORT_B_data_in_reg, DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, DB1_q_a[15]_PORT_B_write_enable_reg, , , DB1_q_a[15]_clock_0, DB1_q_a[15]_clock_1, , , , );
DB1_q_a[13] = DB1_q_a[15]_PORT_A_data_out[8];

--DB1_q_a[2] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[2] at M4K_X13_Y9
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