step_a.fit.eqn

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_6 is 21mux:65|6 at LC_X15_Y13_N4
--operation mode is normal

C1_6 = Z_F & U5_agb_out;

--M1_acq_trigger_in_reg[5] is sld_signaltap:moto|acq_trigger_in_reg[5] at LC_X15_Y13_N4
--operation mode is normal

M1_acq_trigger_in_reg[5] = AMPP_FUNCTION(clk5, Z_F, U5_agb_out, VCC);


--C2_7 is 21mux:66|7 at LC_X15_Y13_N1
--operation mode is normal

C2_7 = Z_F # !U5_agb_out;


--AB1_cout is FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component|cntr_8f8:auto_generated|cout at LC_X9_Y5_N8
--operation mode is normal

AB1_cout_carry_eqn = (!AB1L63 & AB1L44) # (AB1L63 & AB1L54);
AB1_cout = !AB1_cout_carry_eqn;


--inst5 is inst5 at LC_X6_Y9_N5
--operation mode is normal

inst5_lut_out = GND;
inst5 = DFFEAS(inst5_lut_out, GLOBAL(clk5), VCC, , , CNTT, , , VCC);


--inst7 is inst7 at LC_X6_Y9_N4
--operation mode is normal

inst6_qfbk = inst6;
inst7 = inst6_qfbk & !inst5;

--inst6 is inst6 at LC_X6_Y9_N4
--operation mode is normal

inst6 = DFFEAS(inst7, GLOBAL(clk5), VCC, , , inst5, , , VCC);


--Y1_dffs[15] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[15] at LC_X24_Y4_N2
--operation mode is normal

Y1_dffs[15]_lut_out = GND;
Y1_dffs[15] = DFFEAS(Y1_dffs[15]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[15], , , VCC);


--Y1_dffs[14] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[14] at LC_X23_Y1_N2
--operation mode is normal

Y1_dffs[14]_lut_out = GND;
Y1_dffs[14] = DFFEAS(Y1_dffs[14]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[14], , , VCC);


--Y1_dffs[13] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[13] at LC_X22_Y3_N2
--operation mode is normal

Y1_dffs[13]_lut_out = AB1_safe_q[13];
Y1_dffs[13] = DFFEAS(Y1_dffs[13]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[12] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[12] at LC_X10_Y5_N2
--operation mode is normal

Y1_dffs[12]_lut_out = AB1_safe_q[12];
Y1_dffs[12] = DFFEAS(Y1_dffs[12]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[11] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[11] at LC_X12_Y1_N2
--operation mode is normal

Y1_dffs[11]_lut_out = AB1_safe_q[11];
Y1_dffs[11] = DFFEAS(Y1_dffs[11]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[10] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[10] at LC_X21_Y4_N2
--operation mode is normal

Y1_dffs[10]_lut_out = GND;
Y1_dffs[10] = DFFEAS(Y1_dffs[10]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[10], , , VCC);


--Y1_dffs[9] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[9] at LC_X10_Y5_N4
--operation mode is normal

Y1_dffs[9]_lut_out = AB1_safe_q[9];
Y1_dffs[9] = DFFEAS(Y1_dffs[9]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[8] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[8] at LC_X10_Y3_N2
--operation mode is normal

Y1_dffs[8]_lut_out = GND;
Y1_dffs[8] = DFFEAS(Y1_dffs[8]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[8], , , VCC);


--Y1_dffs[7] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[7] at LC_X9_Y6_N1
--operation mode is normal

Y1_dffs[7]_lut_out = GND;
Y1_dffs[7] = DFFEAS(Y1_dffs[7]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[7], , , VCC);


--Y1_dffs[6] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[6] at LC_X9_Y2_N2
--operation mode is normal

Y1_dffs[6]_lut_out = AB1_safe_q[6];
Y1_dffs[6] = DFFEAS(Y1_dffs[6]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[5] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[5] at LC_X8_Y4_N2
--operation mode is normal

Y1_dffs[5]_lut_out = AB1_safe_q[5];
Y1_dffs[5] = DFFEAS(Y1_dffs[5]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[4] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[4] at LC_X9_Y3_N2
--operation mode is normal

Y1_dffs[4]_lut_out = AB1_safe_q[4];
Y1_dffs[4] = DFFEAS(Y1_dffs[4]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--Y1_dffs[3] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[3] at LC_X9_Y1_N4
--operation mode is normal

Y1_dffs[3]_lut_out = GND;
Y1_dffs[3] = DFFEAS(Y1_dffs[3]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[3], , , VCC);


--Y1_dffs[2] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[2] at LC_X9_Y6_N0
--operation mode is normal

Y1_dffs[2]_lut_out = GND;
Y1_dffs[2] = DFFEAS(Y1_dffs[2]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[2], , , VCC);


--Y1_dffs[1] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[1] at LC_X9_Y1_N2
--operation mode is normal

Y1_dffs[1]_lut_out = GND;
Y1_dffs[1] = DFFEAS(Y1_dffs[1]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , AB1_safe_q[1], , , VCC);


--Y1_dffs[0] is FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[0] at LC_X8_Y1_N2
--operation mode is normal

Y1_dffs[0]_lut_out = AB1_safe_q[0];
Y1_dffs[0] = DFFEAS(Y1_dffs[0]_lut_out, !GLOBAL(V1_TSTEN), VCC, , , , , , );


--K1_CQ[1] is DECD:136|CQ[1] at LC_X16_Y11_N6
--operation mode is normal

K1_CQ[1]_lut_out = !K1_CQ[1];
K1_CQ[1] = DFFEAS(K1_CQ[1]_lut_out, GLOBAL(D_STP), VCC, , K1_CQ[0], , , , );


--K1_CQ[0] is DECD:136|CQ[0] at LC_X16_Y11_N9
--operation mode is normal

K1_CQ[0]_lut_out = !K1_CQ[0];
K1_CQ[0] = DFFEAS(K1_CQ[0]_lut_out, GLOBAL(D_STP), VCC, , , , , , );


--G1_CQ[1] is Dec2:125|CQ[1] at LC_X15_Y10_N5
--operation mode is normal

G1_CQ[1]_lut_out = H1_CQI[1];
G1_CQ[1] = DFFEAS(G1_CQ[1]_lut_out, GLOBAL(clk0), VCC, , , , , , );


--Q1L4 is busmux:41|lpm_mux:$00000|mux_6fc:auto_generated|w_result49w~11 at LC_X15_Y10_N2
--operation mode is normal

Q1L4 = S & (U1_agb_out) # !S & !G1_CQ[1];

--M1_acq_trigger_in_reg[4] is sld_signaltap:moto|acq_trigger_in_reg[4] at LC_X15_Y10_N2