step_a.tan.rpt

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk5                         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; D_STP                        ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clk0                         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk5'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                  ; To                                                                                                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1                                      ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg10                                    ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg9                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg8                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg7                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg6                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg5                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg4                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg3                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg2                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg1                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_address_reg0                                     ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;
; N/A                                     ; 173.19 MHz ( period = 5.774 ns )                    ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg0                                      ; clk5       ; clk5     ; None                        ; None                      ; 5.481 ns                ;