step_a.tan.rpt

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                                  ; To                                                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.520 ns                                       ; u_d                                                                                                                                                                   ; CNT24:127|CQI[4]                                                                                                                    ;                              ; clk0                         ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 16.533 ns                                      ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg14                                  ; Y[2]                                                                                                                                ; clk0                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 12.809 ns                                      ; S                                                                                                                                                                     ; Y[0]                                                                                                                                ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.562 ns                                       ; altera_internal_jtag                                                                                                                                                  ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]                                                                             ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 7.963 ns                                       ; Dec2:125|CQ[1]                                                                                                                                                        ; Y[1]                                                                                                                                ; clk0                         ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                                       ; altera_internal_jtag~TDO                                                                                                                                              ; altera_reserved_tdo                                                                                                                 ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 128.60 MHz ( period = 7.776 ns )               ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                               ; sld_hub:sld_hub_inst|hub_tdo                                                                                                        ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk5'                         ; N/A   ; None          ; 173.19 MHz ( period = 5.774 ns )               ; sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] ; sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg0    ; clk5                         ; clk5                         ; 0            ;
; Clock Setup: 'clk0'                         ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns )               ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg0                                   ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg0 ; clk0                         ; clk0                         ; 0            ;
; Clock Setup: 'D_STP'                        ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DECD:136|CQ[0]                                                                                                                                                        ; DECD:136|CQ[1]                                                                                                                      ; D_STP                        ; D_STP                        ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                                                                                                                       ;                                                                                                                                     ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0.0NS              ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;