step_a.tan.summary

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.520 ns
From           : u_d
To             : CNT24:127|CQI[4]
From Clock     : 
To Clock       : clk0
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.533 ns
From           : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg14
To             : Y[2]
From Clock     : clk0
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.809 ns
From           : S
To             : Y[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.562 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.963 ns
From           : Dec2:125|CQ[1]
To             : Y[1]
From Clock     : clk0
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 128.60 MHz ( period = 7.776 ns )
From           : sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk5'
Slack          : N/A
Required Time  : None
Actual Time    : 173.19 MHz ( period = 5.774 ns )
From           : sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2]
To             : sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg0
From Clock     : clk5
To Clock       : clk5
Failed Paths   : 0

Type           : Clock Setup: 'clk0'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg0
To             : rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg0
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'D_STP'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : DECD:136|CQ[0]
To             : DECD:136|CQ[1]
From Clock     : D_STP
To Clock       : D_STP
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------