step_a.map.eqn

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

N1L51 = AMPP_FUNCTION(AC6_Q[1], AC2_Q[3], AC2_Q[5], N1L41);


--AC7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal

AC7_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, AC8_Q[8], VCC, N1L62);


--FB3_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]
--operation mode is normal

FB3_WORD_SR[0] = AMPP_FUNCTION(A1L5, FB3L32, FB3L42, FB3_WORD_SR[1], FB3_word_counter[0], !FB2_clear_signal, CC1_state[4], N1L4);


--N1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG
--operation mode is normal

N1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, altera_internal_jtag, CC1_state[4], VCC);


--DC1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[0]
--operation mode is normal

DC1_dffe1a[0] = AMPP_FUNCTION(A1L5, N1L43, AC8_Q[2], AC8_Q[1], AC8_Q[3], !N1L2, N1L8);


--N1L61 is sld_hub:sld_hub_inst|hub_tdo~527
--operation mode is normal

N1L61 = AMPP_FUNCTION(FB3_WORD_SR[0], N1_HUB_BYPASS_REG, DC1_dffe1a[0]);


--N1L71 is sld_hub:sld_hub_inst|hub_tdo~528
--operation mode is normal

N1L71 = AMPP_FUNCTION(AC7_Q[0], N1L61, N1_jtag_debug_mode_usr1);


--KB1_dffs[0] is sld_signaltap:moto|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0]
--operation mode is normal

KB1_dffs[0] = AMPP_FUNCTION(A1L5, KB1_dffs[1], JB1_is_buffer_wrapped_once, CC1_state[4], M1L22, !M1_reset_all);


--KB3_dffs[0] is sld_signaltap:moto|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0]
--operation mode is normal

KB3_dffs[0] = AMPP_FUNCTION(A1L5, KB3_dffs[1], !M1_reset_all, HB1_trigger_setup_ena);


--N1L81 is sld_hub:sld_hub_inst|hub_tdo~529
--operation mode is normal

N1L81 = AMPP_FUNCTION(AC2_Q[4], KB1_dffs[0], AC2_Q[3], KB3_dffs[0]);


--N1L91 is sld_hub:sld_hub_inst|hub_tdo~530
--operation mode is normal

N1L91 = AMPP_FUNCTION(AC6_Q[1], N1_jtag_debug_mode_usr1, N1L81);


--AC8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]
--operation mode is normal

AC8_Q[0] = AMPP_FUNCTION(A1L5, HB1L3, EB1_is_in_use_reg, AC8_Q[1], N1L52, !N1L2, CC1_state[4], AC8L4);


--FB2_WORD_SR[0] is sld_signaltap:moto|sld_rom_sr:crc_rom_sr|WORD_SR[0]
--operation mode is normal

FB2_WORD_SR[0] = AMPP_FUNCTION(A1L5, FB2L61, FB2_word_counter[0], FB2_WORD_SR[1], FB2_word_counter[2], !FB2_clear_signal, CC1_state[4], M1L02);


--N1L02 is sld_hub:sld_hub_inst|hub_tdo~531
--operation mode is normal

N1L02 = AMPP_FUNCTION(AC6_Q[1], FB2_WORD_SR[0], AC2_Q[5]);


--N1L12 is sld_hub:sld_hub_inst|hub_tdo~532
--operation mode is normal

N1L12 = AMPP_FUNCTION(N1_jtag_debug_mode_usr1, AC8_Q[0], N1L02);


--N1L22 is sld_hub:sld_hub_inst|hub_tdo~533
--operation mode is normal

N1L22 = AMPP_FUNCTION(N1L51, N1L71, N1L91, N1L12);


--FB1_WORD_SR[0] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]
--operation mode is normal

FB1_WORD_SR[0] = AMPP_FUNCTION(A1L5, FB1L32, FB1L42, FB1_WORD_SR[1], FB1_word_counter[0], !FB2_clear_signal, CC1_state[4], EB1L9);


--AC1_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
--operation mode is normal

AC1_Q[1] = AMPP_FUNCTION(A1L5, AC3_Q[1], AC8_Q[1], AC5_Q[0], !N1L2, N1L82);


--AC1L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~47
--operation mode is normal

AC1L4 = AMPP_FUNCTION(AC1_Q[2], AC1_Q[1]);


--EB1_bypass_reg_out is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out
--operation mode is normal

EB1_bypass_reg_out = AMPP_FUNCTION(A1L5, altera_internal_jtag, !N1L2, N1L63);


--AC1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]
--operation mode is normal

AC1_Q[0] = AMPP_FUNCTION(A1L5, AC3_Q[0], AC8_Q[0], AC5_Q[0], !N1L2, N1L82);


--N1L32 is sld_hub:sld_hub_inst|hub_tdo~534
--operation mode is normal

N1L32 = AMPP_FUNCTION(FB1_WORD_SR[0], AC1L4, EB1_bypass_reg_out, AC1_Q[0]);


--EB1_ram_rom_data_reg[0] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

EB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, DB1_q_b[0], EB1_ram_rom_data_reg[1], EB1L11, VCC, EB1L14);


--N1L42 is sld_hub:sld_hub_inst|hub_tdo~535
--operation mode is normal

N1L42 = AMPP_FUNCTION(N1L32, EB1_ram_rom_data_reg[0], AC1L4, AC1_Q[0]);


--CC1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
--operation mode is normal

CC1_state[8] = AMPP_FUNCTION(A1L5, CC1_state[5], CC1_state[7], VCC, !A1L7);


--CC1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal

CC1_state[4] = AMPP_FUNCTION(A1L5, CC1_state[7], CC1_state[3], CC1_state[4], VCC, A1L7);


--CC1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal

CC1_state[3] = AMPP_FUNCTION(A1L5, CC1_state[2], A1L7, VCC);


--CC1L81 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13
--operation mode is normal

CC1L81 = AMPP_FUNCTION(CC1_state[4], CC1_state[3]);


--U5_lcarry[0] is cmp3:131|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[0]
--operation mode is arithmetic

U5_lcarry[0] = CARRY(K1L5 & !D1_CQI[1]);


--D1_CQI[2] is CNT8:83|CQI[2]
--operation mode is arithmetic

D1_CQI[2]_carry_eqn = D1L5;
D1_CQI[2]_lut_out = D1_CQI[2] $ (!D1_CQI[2]_carry_eqn);
D1_CQI[2] = DFFEAS(D1_CQI[2]_lut_out, clk5, VCC, , , , , , );

--D1L7 is CNT8:83|CQI[2]~44
--operation mode is arithmetic

D1L7 = CARRY(D1_CQI[2] & (!D1L5));


--K1L4 is DECD:136|D[2]~42
--operation mode is normal

K1L4 = K1_CQ[0] # !K1L5;


--U1_lcarry[0] is cmp3:93|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[0]
--operation mode is arithmetic

U1_lcarry[0] = CARRY(DB1_q_a[12] & !D1_CQI[1]);


--DB1_q_a[13] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[13]_PORT_A_data_in = VCC;
DB1_q_a[13]_PORT_A_data_in_reg = DFFE(DB1_q_a[13]_PORT_A_data_in, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_B_data_in = EB1_ram_rom_data_reg[13];
DB1_q_a[13]_PORT_B_data_in_reg = DFFE(DB1_q_a[13]_PORT_B_data_in, DB1_q_a[13]_clock_1, , , );
DB1_q_a[13]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[13]_PORT_A_address_reg = DFFE(DB1_q_a[13]_PORT_A_address, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[13]_PORT_B_address_reg = DFFE(DB1_q_a[13]_PORT_B_address, DB1_q_a[13]_clock_1, , , );
DB1_q_a[13]_PORT_A_write_enable = GND;
DB1_q_a[13]_PORT_A_write_enable_reg = DFFE(DB1_q_a[13]_PORT_A_write_enable, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_B_write_enable = EB1L2;
DB1_q_a[13]_PORT_B_write_enable_reg = DFFE(DB1_q_a[13]_PORT_B_write_enable, DB1_q_a[13]_clock_1, , , );
DB1_q_a[13]_clock_0 = clk0;
DB1_q_a[13]_clock_1 = A1L5;
DB1_q_a[13]_PORT_A_data_out = MEMORY(DB1_q_a[13]_PORT_A_data_in_reg, DB1_q_a[13]_PORT_B_data_in_reg, DB1_q_a[13]_PORT_A_address_reg, DB1_q_a[13]_PORT_B_address_reg, DB1_q_a[13]_PORT_A_write_enable_reg, DB1_q_a[13]_PORT_B_write_enable_reg, , , DB1_q_a[13]_clock_0, DB1_q_a[13]_clock_1, , , , );
DB1_q_a[13] = DB1_q_a[13]_PORT_A_data_out[0];

--DB1_q_b[13] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[13]
DB1_q_b[13]_PORT_A_data_in = VCC;
DB1_q_b[13]_PORT_A_data_in_reg = DFFE(DB1_q_b[13]_PORT_A_data_in, DB1_q_b[13]_clock_0, , , );
DB1_q_b[13]_PORT_B_data_in = EB1_ram_rom_data_reg[13];
DB1_q_b[13]_PORT_B_data_in_reg = DFFE(DB1_q_b[13]_PORT_B_data_in, DB1_q_b[13]_clock_1, , , );
DB1_q_b[13]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[13]_PORT_A_address_reg = DFFE(DB1_q_b[13]_PORT_A_address, DB1_q_b[13]_clock_0, , , );
DB1_q_b[13]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[13]_PORT_B_address_reg = DFFE(DB1_q_b[13]_PORT_B_address, DB1_q_b[13]_clock_1, , , );
DB1_q_b[13]_PORT_A_write_enable = GND;
DB1_q_b[13]_PORT_A_write_enable_reg = DFFE(DB1_q_b[13]_PORT_A_write_enable, DB1_q_b[13]_clock_0, , , );
DB1_q_b[13]_PORT_B_write_enable = EB1L2;
DB1_q_b[13]_PORT_B_write_enable_reg = DFFE(DB1_q_b[13]_PORT_B_write_enable, DB1_q_b[13]_clock_1, , , );
DB1_q_b[13]_clock_0 = clk0;
DB1_q_b[13]_clock_1 = A1L5;
DB1_q_b[13]_PORT_B_data_out = MEMORY(DB1_q_b[13]_PORT_A_data_in_reg, DB1_q_b[13]_PORT_B_data_in_reg, DB1_q_b[13]_PORT_A_address_reg, DB1_q_b[13]_PORT_B_address_reg, DB1_q_b[13]_PORT_A_write_enable_reg, DB1_q_b[13]_PORT_B_write_enable_reg, , , DB1_q_b[13]_clock_0, DB1_q_b[13]_clock_1, , , , );
DB1_q_b[13] = DB1_q_b[13]_PORT_B_data_out[0];


--EB1_ram_rom_data_reg[14] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[14]
--operation mode is normal

EB1_ram_rom_data_reg[14] = AMPP_FUNCTION(A1L5, DB1_q_b[14], EB1_ram_rom_data_reg[15], EB1L11, VCC, EB1L14);


--AC3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

AC3_Q[2] = AMPP_FUNCTION(A1L5, AC8_Q[2], !N1L2, N1L01);


--AC8_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

AC8_Q[2] = AMPP_FUNCTION(A1L5, HB1L5, EB1_ir_loaded_address_reg[1], AC8_Q[3], N1L52, !N1L2, CC1_state[4], AC8L4);


--CC1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal

CC1_state[1] = AMPP_FUNCTION(A1L5, CC1_state[0], CC1_state[8], CC1_state[1], CC1_state[15], VCC, A1L7);


--AC9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
--operation mode is normal

AC9_Q[0] = AMPP_FUNCTION(A1L5, DC1_dffe1a[7], N1_jtag_debug_mode_usr1, N1L3);


--N1L2 is sld_hub:sld_hub_inst|CLEAR_SIGNAL~0
--operation mode is normal

N1L2 = AMPP_FUNCTION(CC1_state[1], AC9_Q[0]);


--N1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

N1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, N1_jtag_debug_mode_usr1,