step_a.map.eqn

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

--operation mode is arithmetic

H1_CQI[3]_carry_eqn = H1L7;
H1_CQI[3]_lut_out = u_d $ H1_CQI[3] $ H1_CQI[3]_carry_eqn;
H1_CQI[3] = DFFEAS(H1_CQI[3]_lut_out, clk0, VCC, , , , , , );

--H1L9 is CNT24:127|CQI[3]~59
--operation mode is arithmetic

H1L9 = CARRY(u_d & H1_CQI[3] & !H1L7 # !u_d & (H1_CQI[3] # !H1L7));


--H1_CQI[4] is CNT24:127|CQI[4]
--operation mode is normal

H1_CQI[4]_carry_eqn = H1L9;
H1_CQI[4]_lut_out = u_d $ H1_CQI[4] $ !H1_CQI[4]_carry_eqn;
H1_CQI[4] = DFFEAS(H1_CQI[4]_lut_out, clk0, VCC, , , , , , );


--EB1_ram_rom_data_reg[15] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[15]
--operation mode is normal

EB1_ram_rom_data_reg[15] = AMPP_FUNCTION(A1L5, DB1_q_b[15], altera_internal_jtag, EB1L11, VCC, EB1L14);


--EB1_ram_rom_addr_reg[0] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]
--operation mode is arithmetic

EB1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L5, EB1_ram_rom_incr_addr, EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], !AC1_Q[0], EB1L01);

--EB1L61 is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~71
--operation mode is arithmetic

EB1L61 = AMPP_FUNCTION(EB1_ram_rom_incr_addr, EB1_ram_rom_addr_reg[0]);


--EB1_ram_rom_addr_reg[1] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]
--operation mode is arithmetic

EB1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L5, EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], !AC1_Q[0], EB1L01, EB1L61);

--EB1L81 is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~75
--operation mode is arithmetic

EB1L81 = AMPP_FUNCTION(EB1_ram_rom_addr_reg[1], EB1L61);


--EB1_ram_rom_addr_reg[2] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]
--operation mode is arithmetic

EB1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L5, EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], !AC1_Q[0], EB1L01, EB1L81);

--EB1L02 is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~79
--operation mode is arithmetic

EB1L02 = AMPP_FUNCTION(EB1_ram_rom_addr_reg[2], EB1L81);


--EB1_ram_rom_addr_reg[3] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]
--operation mode is arithmetic

EB1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L5, EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4], !AC1_Q[0], EB1L01, EB1L02);

--EB1L22 is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~83
--operation mode is arithmetic

EB1L22 = AMPP_FUNCTION(EB1_ram_rom_addr_reg[3], EB1L02);


--EB1_ram_rom_addr_reg[4] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]
--operation mode is normal

EB1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L5, EB1_ram_rom_addr_reg[4], altera_internal_jtag, !AC1_Q[0], EB1L01, EB1L22);


--H1L4 is CNT24:127|CQI[1]~68
--operation mode is arithmetic

H1L4 = CARRY(u_d & !inst8 & !H1L5 # !u_d & (!H1L5 # !inst8));


--U2_lcarry[1] is cmp3:94|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[1]
--operation mode is arithmetic

U2_lcarry[1] = CARRY(DB1_q_a[9] & D1_CQI[2] & !U2_lcarry[0] # !DB1_q_a[9] & (D1_CQI[2] # !U2_lcarry[0]));


--DB1_q_a[10] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[10]_PORT_A_data_in = VCC;
DB1_q_a[10]_PORT_A_data_in_reg = DFFE(DB1_q_a[10]_PORT_A_data_in, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_B_data_in = EB1_ram_rom_data_reg[10];
DB1_q_a[10]_PORT_B_data_in_reg = DFFE(DB1_q_a[10]_PORT_B_data_in, DB1_q_a[10]_clock_1, , , );
DB1_q_a[10]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[10]_PORT_A_address_reg = DFFE(DB1_q_a[10]_PORT_A_address, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[10]_PORT_B_address_reg = DFFE(DB1_q_a[10]_PORT_B_address, DB1_q_a[10]_clock_1, , , );
DB1_q_a[10]_PORT_A_write_enable = GND;
DB1_q_a[10]_PORT_A_write_enable_reg = DFFE(DB1_q_a[10]_PORT_A_write_enable, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_B_write_enable = EB1L2;
DB1_q_a[10]_PORT_B_write_enable_reg = DFFE(DB1_q_a[10]_PORT_B_write_enable, DB1_q_a[10]_clock_1, , , );
DB1_q_a[10]_clock_0 = clk0;
DB1_q_a[10]_clock_1 = A1L5;
DB1_q_a[10]_PORT_A_data_out = MEMORY(DB1_q_a[10]_PORT_A_data_in_reg, DB1_q_a[10]_PORT_B_data_in_reg, DB1_q_a[10]_PORT_A_address_reg, DB1_q_a[10]_PORT_B_address_reg, DB1_q_a[10]_PORT_A_write_enable_reg, DB1_q_a[10]_PORT_B_write_enable_reg, , , DB1_q_a[10]_clock_0, DB1_q_a[10]_clock_1, , , , );
DB1_q_a[10] = DB1_q_a[10]_PORT_A_data_out[0];

--DB1_q_b[10] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[10]
DB1_q_b[10]_PORT_A_data_in = VCC;
DB1_q_b[10]_PORT_A_data_in_reg = DFFE(DB1_q_b[10]_PORT_A_data_in, DB1_q_b[10]_clock_0, , , );
DB1_q_b[10]_PORT_B_data_in = EB1_ram_rom_data_reg[10];
DB1_q_b[10]_PORT_B_data_in_reg = DFFE(DB1_q_b[10]_PORT_B_data_in, DB1_q_b[10]_clock_1, , , );
DB1_q_b[10]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[10]_PORT_A_address_reg = DFFE(DB1_q_b[10]_PORT_A_address, DB1_q_b[10]_clock_0, , , );
DB1_q_b[10]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[10]_PORT_B_address_reg = DFFE(DB1_q_b[10]_PORT_B_address, DB1_q_b[10]_clock_1, , , );
DB1_q_b[10]_PORT_A_write_enable = GND;
DB1_q_b[10]_PORT_A_write_enable_reg = DFFE(DB1_q_b[10]_PORT_A_write_enable, DB1_q_b[10]_clock_0, , , );
DB1_q_b[10]_PORT_B_write_enable = EB1L2;
DB1_q_b[10]_PORT_B_write_enable_reg = DFFE(DB1_q_b[10]_PORT_B_write_enable, DB1_q_b[10]_clock_1, , , );
DB1_q_b[10]_clock_0 = clk0;
DB1_q_b[10]_clock_1 = A1L5;
DB1_q_b[10]_PORT_B_data_out = MEMORY(DB1_q_b[10]_PORT_A_data_in_reg, DB1_q_b[10]_PORT_B_data_in_reg, DB1_q_b[10]_PORT_A_address_reg, DB1_q_b[10]_PORT_B_address_reg, DB1_q_b[10]_PORT_A_write_enable_reg, DB1_q_b[10]_PORT_B_write_enable_reg, , , DB1_q_b[10]_clock_0, DB1_q_b[10]_clock_1, , , , );
DB1_q_b[10] = DB1_q_b[10]_PORT_B_data_out[0];


--EB1_ram_rom_data_reg[11] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[11]
--operation mode is normal

EB1_ram_rom_data_reg[11] = AMPP_FUNCTION(A1L5, DB1_q_b[11], EB1_ram_rom_data_reg[12], EB1L11, VCC, EB1L14);


--U3_lcarry[1] is cmp3:95|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[1]
--operation mode is arithmetic

U3_lcarry[1] = CARRY(DB1_q_a[5] & D1_CQI[2] & !U3_lcarry[0] # !DB1_q_a[5] & (D1_CQI[2] # !U3_lcarry[0]));


--DB1_q_a[6] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[6]_PORT_A_data_in = VCC;
DB1_q_a[6]_PORT_A_data_in_reg = DFFE(DB1_q_a[6]_PORT_A_data_in, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_B_data_in = EB1_ram_rom_data_reg[6];
DB1_q_a[6]_PORT_B_data_in_reg = DFFE(DB1_q_a[6]_PORT_B_data_in, DB1_q_a[6]_clock_1, , , );
DB1_q_a[6]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[6]_PORT_A_address_reg = DFFE(DB1_q_a[6]_PORT_A_address, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[6]_PORT_B_address_reg = DFFE(DB1_q_a[6]_PORT_B_address, DB1_q_a[6]_clock_1, , , );
DB1_q_a[6]_PORT_A_write_enable = GND;
DB1_q_a[6]_PORT_A_write_enable_reg = DFFE(DB1_q_a[6]_PORT_A_write_enable, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_B_write_enable = EB1L2;
DB1_q_a[6]_PORT_B_write_enable_reg = DFFE(DB1_q_a[6]_PORT_B_write_enable, DB1_q_a[6]_clock_1, , , );
DB1_q_a[6]_clock_0 = clk0;
DB1_q_a[6]_clock_1 = A1L5;
DB1_q_a[6]_PORT_A_data_out = MEMORY(DB1_q_a[6]_PORT_A_data_in_reg, DB1_q_a[6]_PORT_B_data_in_reg, DB1_q_a[6]_PORT_A_address_reg, DB1_q_a[6]_PORT_B_address_reg, DB1_q_a[6]_PORT_A_write_enable_reg, DB1_q_a[6]_PORT_B_write_enable_reg, , , DB1_q_a[6]_clock_0, DB1_q_a[6]_clock_1, , , , );
DB1_q_a[6] = DB1_q_a[6]_PORT_A_data_out[0];

--DB1_q_b[6] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[6]
DB1_q_b[6]_PORT_A_data_in = VCC;
DB1_q_b[6]_PORT_A_data_in_reg = DFFE(DB1_q_b[6]_PORT_A_data_in, DB1_q_b[6]_clock_0, , , );
DB1_q_b[6]_PORT_B_data_in = EB1_ram_rom_data_reg[6];
DB1_q_b[6]_PORT_B_data_in_reg = DFFE(DB1_q_b[6]_PORT_B_data_in, DB1_q_b[6]_clock_1, , , );
DB1_q_b[6]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[6]_PORT_A_address_reg = DFFE(DB1_q_b[6]_PORT_A_address, DB1_q_b[6]_clock_0, , , );
DB1_q_b[6]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[6]_PORT_B_address_reg = DFFE(DB1_q_b[6]_PORT_B_address, DB1_q_b[6]_clock_1, , , );
DB1_q_b[6]_PORT_A_write_enable = GND;
DB1_q_b[6]_PORT_A_write_enable_reg = DFFE(DB1_q_b[6]_PORT_A_write_enable, DB1_q_b[6]_clock_0, , , );
DB1_q_b[6]_PORT_B_write_enable = EB1L2;
DB1_q_b[6]_PORT_B_write_enable_reg = DFFE(DB1_q_b[6]_PORT_B_write_enable, DB1_q_b[6]_clock_1, , , );
DB1_q_b[6]_clock_0 = clk0;
DB1_q_b[6]_clock_1 = A1L5;
DB1_q_b[6]_PORT_B_data_out = MEMORY(DB1_q_b[6]_PORT_A_data_in_reg, DB1_q_b[6]_PORT_B_data_in_reg, DB1_q_b[6]_PORT_A_address_reg, DB1_q_b[6]_PORT_B_address_reg, DB1_q_b[6]_PORT_A_write_enable_reg, DB1_q_b[6]_PORT_B_write_enable_reg, , , DB1_q_b[6]_clock_0, DB1_q_b[6]_clock_1, , , , );
DB1_q_b[6] = DB1_q_b[6]_PORT_B_data_out[0];


--EB1_ram_rom_data_reg[7] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

EB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, DB1_q_b[7], EB1_ram_rom_data_reg[8], EB1L11, VCC, EB1L14);


--U4_lcarry[1] is cmp3:96|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[1]
--operation mode is arithmetic

U4_lcarry[1] = CARRY(DB1_q_a[1] & D1_CQI[2] & !U4_lcarry[0] # !DB1_q_a[1] & (D1_CQI[2] # !U4_lcarry[0]));


--DB1_q_a[2] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[2]_PORT_A_data_in = VCC;
DB1_q_a[2]_PORT_A_data_in_reg = DFFE(DB1_q_a[2]_PORT_A_data_in, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_B_data_in = EB1_ram_rom_data_reg[2];
DB1_q_a[2]_PORT_B_data_in_reg = DFFE(DB1_q_a[2]_PORT_B_data_in, DB1_q_a[2]_clock_1, , , );
DB1_q_a[2]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[2]_PORT_A_address_reg = DFFE(DB1_q_a[2]_PORT_A_address, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[2]_PORT_B_address_reg = DFFE(DB1_q_a[2]_PORT_B_address, DB1_q_a[2]_clock_1, , , );
DB1_q_a[2]_PORT_A_write_enable = GND;
DB1_q_a[2]_PORT_A_write_enable_reg = DFFE(DB1_q_a[2]_PORT_A_write_enable, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_B_write_enable = EB1L2;
DB1_q_a[2]_PORT_B_write_enable_reg = DFFE(DB1_q_a[2]_PORT_B_write_enable, DB1_q_a[2]_clock_1, , , );
DB1_q_a[2]_clock_0 = clk0;
DB1_q_a[2]_clock_1 = A1L5;
DB1_q_a[2]_PORT_A_data_out = MEMORY(DB1_q_a[2]_PORT_A_data_in_reg, DB1_q_a[2]_PORT_B_data_in_reg, DB1_q_a[2]_PORT_A_address_reg, DB1_q_a[2]_PORT_B_address_reg, DB1_q_a[2]_PORT_A_write_enable_reg, DB1_q_a[2]_PORT_B_write_enable_reg, , , DB1_q_a[2]_clock_0, DB1_q_a[2]_clock_1, , , , );
DB1_q_a[2] = DB1_q_a[2]_PORT_A_data_out[0];

--DB1_q_b[2] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[2]
DB1_q_b[2]_PORT_A_data_in = VCC;
DB1_q_b[2]_PORT_A_data_in_reg = DFFE(DB1_q_b[2]_PORT_A_data_in, DB1_q_b[2]_clock_0, , , );
DB1_q_b[2]_PORT_B_data_in = EB1_ram_rom_data_reg[2];
DB1_q_b[2]_PORT_B_data_in_reg = DFFE(DB1_q_b[2]_PORT_B_data_in, DB1_q_b[2]_clock_1, , , );
DB1_q_b[2]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[2]_PORT_A_address_reg = DFFE(DB1_q_b[2]_PORT_A_address, DB1_q_b[2]_clock_0, , , );
DB1_q_b[2]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[2]_PORT_B_address_reg = DFFE(DB1_q_b[2]_PORT_B_address, DB1_q_b[2]_clock_1, , , );
DB1_q_b[2]_PORT_A_write_enable = GND;
DB1_q_b[2]_PORT_A_write_enable_reg = DFFE(DB1_q_b[2]_PORT_A_write_enable, DB1_q_b[2]_clock_0, , , );
DB1_q_b[2]_PORT_B_write_enable = EB1L2;
DB1_q_b[2]_PORT_B_write_enable_reg = DFFE(DB1_q_b[2]_PORT_B_write_enable, DB1_q_b[2]_clock_1, , , );
DB1_q_b[2]_clock_0 = clk0;
DB1_q_b[2]_clock_1 = A1L5;
DB1_q_b[2]_PORT_B_data_out = MEMORY(DB1_q_b[2]_PORT_A_data_in_reg, DB1_q_b[2]_PORT_B_data_in_reg, DB1_q_b[2]_PORT_A_address_reg, DB1_q_b[2]_PORT_B_address_reg, DB1_q_b[2]_PORT_A_write_enable_reg, DB1_q_b[2]_PORT_B_write_enable_reg, , , DB1_q_b[2]_clock_0, DB1_q_b[2]_clock_1, , , , );
DB1_q_b[2] = DB1_q_b[2]_PORT_B_data_out[0];


--EB1_ram_rom_data_reg[3] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

EB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, DB1_q_b[3], EB1_ram_rom_data_reg[4], EB1L11, VCC, EB1L14);


--AC6_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]
--operation mode is normal

AC6_Q[1] = AMPP_FUNCTION(A1L5, altera_internal_jtag, AC8_Q[8], !N1L2, N1L62);


--AC2_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3]
--operation mode is normal

AC2_Q[3] = AMPP_FUNCTION(A1L5, AC4_Q[3], AC8_Q[3], AC5_Q[0], !N1L2, N1L92);


--AC2_Q[5] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5]
--operation mode is normal

AC2_Q[5] = AMPP_FUNCTION(A1L5, AC4_Q[5], AC8_Q[5], AC5_Q[0], !N1L2, N1L92);


--AC2_Q[4] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[4]
--operation mode is normal

AC2_Q[4] = AMPP_FUNCTION(A1L5, AC4_Q[4], AC8_Q[4], AC5_Q[0], !N1L2, N1L92);


--M1_bypass_reg_out is sld_signaltap:moto|bypass_reg_out
--operation mode is normal

M1_bypass_reg_out = AMPP_FUNCTION(A1L5, altera_internal_jtag, !M1_reset_all, N1L73);


--N1L41 is sld_hub:sld_hub_inst|hub_tdo~525
--operation mode is normal

N1L41 = AMPP_FUNCTION(N1_jtag_debug_mode_usr1, AC2_Q[4], M1_bypass_reg_out);


--N1L51 is sld_hub:sld_hub_inst|hub_tdo~526
--operation mode is normal