step_a.map.eqn

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

DB1_q_b[11]_PORT_A_data_in = VCC;
DB1_q_b[11]_PORT_A_data_in_reg = DFFE(DB1_q_b[11]_PORT_A_data_in, DB1_q_b[11]_clock_0, , , );
DB1_q_b[11]_PORT_B_data_in = EB1_ram_rom_data_reg[11];
DB1_q_b[11]_PORT_B_data_in_reg = DFFE(DB1_q_b[11]_PORT_B_data_in, DB1_q_b[11]_clock_1, , , );
DB1_q_b[11]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[11]_PORT_A_address_reg = DFFE(DB1_q_b[11]_PORT_A_address, DB1_q_b[11]_clock_0, , , );
DB1_q_b[11]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[11]_PORT_B_address_reg = DFFE(DB1_q_b[11]_PORT_B_address, DB1_q_b[11]_clock_1, , , );
DB1_q_b[11]_PORT_A_write_enable = GND;
DB1_q_b[11]_PORT_A_write_enable_reg = DFFE(DB1_q_b[11]_PORT_A_write_enable, DB1_q_b[11]_clock_0, , , );
DB1_q_b[11]_PORT_B_write_enable = EB1L2;
DB1_q_b[11]_PORT_B_write_enable_reg = DFFE(DB1_q_b[11]_PORT_B_write_enable, DB1_q_b[11]_clock_1, , , );
DB1_q_b[11]_clock_0 = clk0;
DB1_q_b[11]_clock_1 = A1L5;
DB1_q_b[11]_PORT_B_data_out = MEMORY(DB1_q_b[11]_PORT_A_data_in_reg, DB1_q_b[11]_PORT_B_data_in_reg, DB1_q_b[11]_PORT_A_address_reg, DB1_q_b[11]_PORT_B_address_reg, DB1_q_b[11]_PORT_A_write_enable_reg, DB1_q_b[11]_PORT_B_write_enable_reg, , , DB1_q_b[11]_clock_0, DB1_q_b[11]_clock_1, , , , );
DB1_q_b[11] = DB1_q_b[11]_PORT_B_data_out[0];


--U2_agb_out is cmp3:94|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|agb_out
--operation mode is normal

U2_agb_out_carry_eqn = U2_lcarry[2];
U2_agb_out = LCELL(DB1_q_a[11] & (U2_agb_out_carry_eqn # !D1_CQI[4]) # !DB1_q_a[11] & U2_agb_out_carry_eqn & !D1_CQI[4]);


--U3_lcarry[2] is cmp3:95|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[2]
--operation mode is arithmetic

U3_lcarry[2] = CARRY(DB1_q_a[6] & (!U3_lcarry[1] # !D1_CQI[3]) # !DB1_q_a[6] & !D1_CQI[3] & !U3_lcarry[1]);


--DB1_q_a[7] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[7]_PORT_A_data_in = VCC;
DB1_q_a[7]_PORT_A_data_in_reg = DFFE(DB1_q_a[7]_PORT_A_data_in, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_B_data_in = EB1_ram_rom_data_reg[7];
DB1_q_a[7]_PORT_B_data_in_reg = DFFE(DB1_q_a[7]_PORT_B_data_in, DB1_q_a[7]_clock_1, , , );
DB1_q_a[7]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[7]_PORT_A_address_reg = DFFE(DB1_q_a[7]_PORT_A_address, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[7]_PORT_B_address_reg = DFFE(DB1_q_a[7]_PORT_B_address, DB1_q_a[7]_clock_1, , , );
DB1_q_a[7]_PORT_A_write_enable = GND;
DB1_q_a[7]_PORT_A_write_enable_reg = DFFE(DB1_q_a[7]_PORT_A_write_enable, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_B_write_enable = EB1L2;
DB1_q_a[7]_PORT_B_write_enable_reg = DFFE(DB1_q_a[7]_PORT_B_write_enable, DB1_q_a[7]_clock_1, , , );
DB1_q_a[7]_clock_0 = clk0;
DB1_q_a[7]_clock_1 = A1L5;
DB1_q_a[7]_PORT_A_data_out = MEMORY(DB1_q_a[7]_PORT_A_data_in_reg, DB1_q_a[7]_PORT_B_data_in_reg, DB1_q_a[7]_PORT_A_address_reg, DB1_q_a[7]_PORT_B_address_reg, DB1_q_a[7]_PORT_A_write_enable_reg, DB1_q_a[7]_PORT_B_write_enable_reg, , , DB1_q_a[7]_clock_0, DB1_q_a[7]_clock_1, , , , );
DB1_q_a[7] = DB1_q_a[7]_PORT_A_data_out[0];

--DB1_q_b[7] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[7]
DB1_q_b[7]_PORT_A_data_in = VCC;
DB1_q_b[7]_PORT_A_data_in_reg = DFFE(DB1_q_b[7]_PORT_A_data_in, DB1_q_b[7]_clock_0, , , );
DB1_q_b[7]_PORT_B_data_in = EB1_ram_rom_data_reg[7];
DB1_q_b[7]_PORT_B_data_in_reg = DFFE(DB1_q_b[7]_PORT_B_data_in, DB1_q_b[7]_clock_1, , , );
DB1_q_b[7]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[7]_PORT_A_address_reg = DFFE(DB1_q_b[7]_PORT_A_address, DB1_q_b[7]_clock_0, , , );
DB1_q_b[7]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[7]_PORT_B_address_reg = DFFE(DB1_q_b[7]_PORT_B_address, DB1_q_b[7]_clock_1, , , );
DB1_q_b[7]_PORT_A_write_enable = GND;
DB1_q_b[7]_PORT_A_write_enable_reg = DFFE(DB1_q_b[7]_PORT_A_write_enable, DB1_q_b[7]_clock_0, , , );
DB1_q_b[7]_PORT_B_write_enable = EB1L2;
DB1_q_b[7]_PORT_B_write_enable_reg = DFFE(DB1_q_b[7]_PORT_B_write_enable, DB1_q_b[7]_clock_1, , , );
DB1_q_b[7]_clock_0 = clk0;
DB1_q_b[7]_clock_1 = A1L5;
DB1_q_b[7]_PORT_B_data_out = MEMORY(DB1_q_b[7]_PORT_A_data_in_reg, DB1_q_b[7]_PORT_B_data_in_reg, DB1_q_b[7]_PORT_A_address_reg, DB1_q_b[7]_PORT_B_address_reg, DB1_q_b[7]_PORT_A_write_enable_reg, DB1_q_b[7]_PORT_B_write_enable_reg, , , DB1_q_b[7]_clock_0, DB1_q_b[7]_clock_1, , , , );
DB1_q_b[7] = DB1_q_b[7]_PORT_B_data_out[0];


--U3_agb_out is cmp3:95|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|agb_out
--operation mode is normal

U3_agb_out_carry_eqn = U3_lcarry[2];
U3_agb_out = LCELL(DB1_q_a[7] & (U3_agb_out_carry_eqn # !D1_CQI[4]) # !DB1_q_a[7] & U3_agb_out_carry_eqn & !D1_CQI[4]);


--U4_lcarry[2] is cmp3:96|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[2]
--operation mode is arithmetic

U4_lcarry[2] = CARRY(DB1_q_a[2] & (!U4_lcarry[1] # !D1_CQI[3]) # !DB1_q_a[2] & !D1_CQI[3] & !U4_lcarry[1]);


--DB1_q_a[3] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[3]_PORT_A_data_in = VCC;
DB1_q_a[3]_PORT_A_data_in_reg = DFFE(DB1_q_a[3]_PORT_A_data_in, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_B_data_in = EB1_ram_rom_data_reg[3];
DB1_q_a[3]_PORT_B_data_in_reg = DFFE(DB1_q_a[3]_PORT_B_data_in, DB1_q_a[3]_clock_1, , , );
DB1_q_a[3]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[3]_PORT_A_address_reg = DFFE(DB1_q_a[3]_PORT_A_address, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[3]_PORT_B_address_reg = DFFE(DB1_q_a[3]_PORT_B_address, DB1_q_a[3]_clock_1, , , );
DB1_q_a[3]_PORT_A_write_enable = GND;
DB1_q_a[3]_PORT_A_write_enable_reg = DFFE(DB1_q_a[3]_PORT_A_write_enable, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_B_write_enable = EB1L2;
DB1_q_a[3]_PORT_B_write_enable_reg = DFFE(DB1_q_a[3]_PORT_B_write_enable, DB1_q_a[3]_clock_1, , , );
DB1_q_a[3]_clock_0 = clk0;
DB1_q_a[3]_clock_1 = A1L5;
DB1_q_a[3]_PORT_A_data_out = MEMORY(DB1_q_a[3]_PORT_A_data_in_reg, DB1_q_a[3]_PORT_B_data_in_reg, DB1_q_a[3]_PORT_A_address_reg, DB1_q_a[3]_PORT_B_address_reg, DB1_q_a[3]_PORT_A_write_enable_reg, DB1_q_a[3]_PORT_B_write_enable_reg, , , DB1_q_a[3]_clock_0, DB1_q_a[3]_clock_1, , , , );
DB1_q_a[3] = DB1_q_a[3]_PORT_A_data_out[0];

--DB1_q_b[3] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[3]
DB1_q_b[3]_PORT_A_data_in = VCC;
DB1_q_b[3]_PORT_A_data_in_reg = DFFE(DB1_q_b[3]_PORT_A_data_in, DB1_q_b[3]_clock_0, , , );
DB1_q_b[3]_PORT_B_data_in = EB1_ram_rom_data_reg[3];
DB1_q_b[3]_PORT_B_data_in_reg = DFFE(DB1_q_b[3]_PORT_B_data_in, DB1_q_b[3]_clock_1, , , );
DB1_q_b[3]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[3]_PORT_A_address_reg = DFFE(DB1_q_b[3]_PORT_A_address, DB1_q_b[3]_clock_0, , , );
DB1_q_b[3]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[3]_PORT_B_address_reg = DFFE(DB1_q_b[3]_PORT_B_address, DB1_q_b[3]_clock_1, , , );
DB1_q_b[3]_PORT_A_write_enable = GND;
DB1_q_b[3]_PORT_A_write_enable_reg = DFFE(DB1_q_b[3]_PORT_A_write_enable, DB1_q_b[3]_clock_0, , , );
DB1_q_b[3]_PORT_B_write_enable = EB1L2;
DB1_q_b[3]_PORT_B_write_enable_reg = DFFE(DB1_q_b[3]_PORT_B_write_enable, DB1_q_b[3]_clock_1, , , );
DB1_q_b[3]_clock_0 = clk0;
DB1_q_b[3]_clock_1 = A1L5;
DB1_q_b[3]_PORT_B_data_out = MEMORY(DB1_q_b[3]_PORT_A_data_in_reg, DB1_q_b[3]_PORT_B_data_in_reg, DB1_q_b[3]_PORT_A_address_reg, DB1_q_b[3]_PORT_B_address_reg, DB1_q_b[3]_PORT_A_write_enable_reg, DB1_q_b[3]_PORT_B_write_enable_reg, , , DB1_q_b[3]_clock_0, DB1_q_b[3]_clock_1, , , , );
DB1_q_b[3] = DB1_q_b[3]_PORT_B_data_out[0];


--U4_agb_out is cmp3:96|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|agb_out
--operation mode is normal

U4_agb_out_carry_eqn = U4_lcarry[2];
U4_agb_out = LCELL(DB1_q_a[3] & (U4_agb_out_carry_eqn # !D1_CQI[4]) # !DB1_q_a[3] & U4_agb_out_carry_eqn & !D1_CQI[4]);


--N1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal

N1_hub_tdo = AMPP_FUNCTION(!A1L5, N1L22, AC6_Q[0], N1L42, N1_jtag_debug_mode_usr1, !CC1_state[8], CC1L81);


--U5_lcarry[1] is cmp3:131|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[1]
--operation mode is arithmetic

U5_lcarry[1] = CARRY(K1L5 & D1_CQI[2] & !U5_lcarry[0] # !K1L5 & (D1_CQI[2] # !U5_lcarry[0]));


--D1_CQI[3] is CNT8:83|CQI[3]
--operation mode is arithmetic

D1_CQI[3]_carry_eqn = D1L7;
D1_CQI[3]_lut_out = D1_CQI[3] $ (D1_CQI[3]_carry_eqn);
D1_CQI[3] = DFFEAS(D1_CQI[3]_lut_out, clk5, VCC, , , , , , );

--D1L9 is CNT8:83|CQI[3]~40
--operation mode is arithmetic

D1L9 = CARRY(!D1L7 # !D1_CQI[3]);


--inst9 is inst9
--operation mode is normal

inst9_lut_out = !inst9;
inst9 = DFFEAS(inst9_lut_out, inst8, VCC, , , , , , );


--V1_CLR_CNT is FREQTEST:121|TESTCTL:U1|CLR_CNT
--operation mode is normal

V1_CLR_CNT = !V1_TSTEN & !inst9;


--U1_lcarry[1] is cmp3:93|lpm_compare:1|comptree:comparator|cmpchain:cmp_end|lcarry[1]
--operation mode is arithmetic

U1_lcarry[1] = CARRY(DB1_q_a[13] & D1_CQI[2] & !U1_lcarry[0] # !DB1_q_a[13] & (D1_CQI[2] # !U1_lcarry[0]));


--DB1_q_a[14] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
DB1_q_a[14]_PORT_A_data_in = VCC;
DB1_q_a[14]_PORT_A_data_in_reg = DFFE(DB1_q_a[14]_PORT_A_data_in, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_B_data_in = EB1_ram_rom_data_reg[14];
DB1_q_a[14]_PORT_B_data_in_reg = DFFE(DB1_q_a[14]_PORT_B_data_in, DB1_q_a[14]_clock_1, , , );
DB1_q_a[14]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_a[14]_PORT_A_address_reg = DFFE(DB1_q_a[14]_PORT_A_address, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_a[14]_PORT_B_address_reg = DFFE(DB1_q_a[14]_PORT_B_address, DB1_q_a[14]_clock_1, , , );
DB1_q_a[14]_PORT_A_write_enable = GND;
DB1_q_a[14]_PORT_A_write_enable_reg = DFFE(DB1_q_a[14]_PORT_A_write_enable, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_B_write_enable = EB1L2;
DB1_q_a[14]_PORT_B_write_enable_reg = DFFE(DB1_q_a[14]_PORT_B_write_enable, DB1_q_a[14]_clock_1, , , );
DB1_q_a[14]_clock_0 = clk0;
DB1_q_a[14]_clock_1 = A1L5;
DB1_q_a[14]_PORT_A_data_out = MEMORY(DB1_q_a[14]_PORT_A_data_in_reg, DB1_q_a[14]_PORT_B_data_in_reg, DB1_q_a[14]_PORT_A_address_reg, DB1_q_a[14]_PORT_B_address_reg, DB1_q_a[14]_PORT_A_write_enable_reg, DB1_q_a[14]_PORT_B_write_enable_reg, , , DB1_q_a[14]_clock_0, DB1_q_a[14]_clock_1, , , , );
DB1_q_a[14] = DB1_q_a[14]_PORT_A_data_out[0];

--DB1_q_b[14] is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[14]
DB1_q_b[14]_PORT_A_data_in = VCC;
DB1_q_b[14]_PORT_A_data_in_reg = DFFE(DB1_q_b[14]_PORT_A_data_in, DB1_q_b[14]_clock_0, , , );
DB1_q_b[14]_PORT_B_data_in = EB1_ram_rom_data_reg[14];
DB1_q_b[14]_PORT_B_data_in_reg = DFFE(DB1_q_b[14]_PORT_B_data_in, DB1_q_b[14]_clock_1, , , );
DB1_q_b[14]_PORT_A_address = BUS(inst8, H1_CQI[1], H1_CQI[2], H1_CQI[3], H1_CQI[4]);
DB1_q_b[14]_PORT_A_address_reg = DFFE(DB1_q_b[14]_PORT_A_address, DB1_q_b[14]_clock_0, , , );
DB1_q_b[14]_PORT_B_address = BUS(EB1_ram_rom_addr_reg[0], EB1_ram_rom_addr_reg[1], EB1_ram_rom_addr_reg[2], EB1_ram_rom_addr_reg[3], EB1_ram_rom_addr_reg[4]);
DB1_q_b[14]_PORT_B_address_reg = DFFE(DB1_q_b[14]_PORT_B_address, DB1_q_b[14]_clock_1, , , );
DB1_q_b[14]_PORT_A_write_enable = GND;
DB1_q_b[14]_PORT_A_write_enable_reg = DFFE(DB1_q_b[14]_PORT_A_write_enable, DB1_q_b[14]_clock_0, , , );
DB1_q_b[14]_PORT_B_write_enable = EB1L2;
DB1_q_b[14]_PORT_B_write_enable_reg = DFFE(DB1_q_b[14]_PORT_B_write_enable, DB1_q_b[14]_clock_1, , , );
DB1_q_b[14]_clock_0 = clk0;
DB1_q_b[14]_clock_1 = A1L5;
DB1_q_b[14]_PORT_B_data_out = MEMORY(DB1_q_b[14]_PORT_A_data_in_reg, DB1_q_b[14]_PORT_B_data_in_reg, DB1_q_b[14]_PORT_A_address_reg, DB1_q_b[14]_PORT_B_address_reg, DB1_q_b[14]_PORT_A_write_enable_reg, DB1_q_b[14]_PORT_B_write_enable_reg, , , DB1_q_b[14]_clock_0, DB1_q_b[14]_clock_1, , , , );
DB1_q_b[14] = DB1_q_b[14]_PORT_B_data_out[0];


--CC1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

CC1_state[5] = AMPP_FUNCTION(A1L5, A1L7, CC1_state[4], CC1_state[3], VCC);


--AC1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

AC1_Q[2] = AMPP_FUNCTION(A1L5, AC3_Q[2], AC8_Q[2], AC5_Q[0], !N1L2, N1L82);


--N1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

N1_jtag_debug_mode = AMPP_FUNCTION(A1L5, N1L43, N1_jtag_debug_mode, N1L53, CC1_state[15], CC1_state[0]);


--AC6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

AC6_Q[0] = AMPP_FUNCTION(A1L5, AC8_Q[8], altera_internal_jtag, !N1L2, N1L62);


--AC5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

AC5_Q[0] = AMPP_FUNCTION(A1L5, DC1_dffe1a[1], !N1L2, N1L1);


--N1L63 is sld_hub:sld_hub_inst|node_ena~40
--operation mode is normal

N1L63 = AMPP_FUNCTION(N1_jtag_debug_mode, AC6_Q[0], AC5_Q[0]);


--N1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

N1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, KB5_dffs[0], KB5_dffs[1], N1L04, N1L14, CC1_state[0], CC1_state[12]);


--EB1L2 is rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

EB1L2 = AMPP_FUNCTION(CC1_state[5], AC1_Q[2], N1L63, N1_jtag_debug_mode_usr1);


--H1_CQI[2] is CNT24:127|CQI[2]
--operation mode is arithmetic

H1_CQI[2]_carry_eqn = H1L3;
H1_CQI[2]_lut_out = u_d $ H1_CQI[2] $ !H1_CQI[2]_carry_eqn;
H1_CQI[2] = DFFEAS(H1_CQI[2]_lut_out, clk0, VCC, , , , , , );

--H1L7 is CNT24:127|CQI[2]~55
--operation mode is arithmetic

H1L7 = CARRY(u_d & (!H1L3 # !H1_CQI[2]) # !u_d & !H1_CQI[2] & !H1L3);


--H1_CQI[3] is CNT24:127|CQI[3]