step_a.hier_info

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

data[1][2] => mux_6fc:auto_generated.data[6]
data[1][3] => mux_6fc:auto_generated.data[7]
sel[0] => mux_6fc:auto_generated.sel[0]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_6fc:auto_generated.result[0]
result[1] <= mux_6fc:auto_generated.result[1]
result[2] <= mux_6fc:auto_generated.result[2]
result[3] <= mux_6fc:auto_generated.result[3]


|step_a|BUSMUX:41|lpm_mux:$00000|mux_6fc:auto_generated
result[0] <= w_result11w.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= w_result25w.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= w_result37w.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= w_result49w.DB_MAX_OUTPUT_PORT_TYPE


|step_a|Dec2:125
CLK => CQ[0].CLK
CLK => CQ[1].CLK
A[0] => CQ[0].DATAIN
A[1] => CQ[1].DATAIN
D[0] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
D[1] <= CQ[1].DB_MAX_OUTPUT_PORT_TYPE
D[2] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
D[3] <= CQ[1].DB_MAX_OUTPUT_PORT_TYPE


|step_a|CNT24:127
CLK => CQI[3].CLK
CLK => CQI[2].CLK
CLK => CQI[1].CLK
CLK => CQI[0].CLK
CLK => CQI[4].CLK
EN => CQI[3].ENA
EN => CQI[2].ENA
EN => CQI[1].ENA
EN => CQI[0].ENA
EN => CQI[4].ENA
U_D => CQI~0.OUTPUTSELECT
U_D => CQI~1.OUTPUTSELECT
U_D => CQI~2.OUTPUTSELECT
U_D => CQI~3.OUTPUTSELECT
U_D => CQI~4.OUTPUTSELECT
CQ[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
CQ[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
CQ[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
CQ[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
CQ[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:93
agb <= LPM_COMPARE:1.agb
a[0] => LPM_COMPARE:1.dataa[0]
a[1] => LPM_COMPARE:1.dataa[1]
a[2] => LPM_COMPARE:1.dataa[2]
a[3] => LPM_COMPARE:1.dataa[3]
b[0] => LPM_COMPARE:1.datab[0]
b[1] => LPM_COMPARE:1.datab[1]
b[2] => LPM_COMPARE:1.datab[2]
b[3] => LPM_COMPARE:1.datab[3]


|step_a|cmp3:93|LPM_COMPARE:1
dataa[0] => comptree:comparator.dataa[0]
dataa[1] => comptree:comparator.dataa[1]
dataa[2] => comptree:comparator.dataa[2]
dataa[3] => comptree:comparator.dataa[3]
datab[0] => comptree:comparator.datab[0]
datab[1] => comptree:comparator.datab[1]
datab[2] => comptree:comparator.datab[2]
datab[3] => comptree:comparator.datab[3]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_xnode.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_xnode.DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:93|LPM_COMPARE:1|comptree:comparator
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
dataa[2] => cmpchain:cmp_end.dataa[2]
dataa[3] => cmpchain:cmp_end.dataa[3]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
datab[2] => cmpchain:cmp_end.datab[2]
datab[3] => cmpchain:cmp_end.datab[3]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= <GND>
agb <= cmpchain:cmp_end.agb


|step_a|cmp3:93|LPM_COMPARE:1|comptree:comparator|cmpchain:cmp_end
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:93|LPM_COMPARE:1|altshift:aeb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:93|LPM_COMPARE:1|altshift:agb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|step_a|rom3:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]


|step_a|rom3:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_0fs:auto_generated.address_a[0]
address_a[1] => altsyncram_0fs:auto_generated.address_a[1]
address_a[2] => altsyncram_0fs:auto_generated.address_a[2]
address_a[3] => altsyncram_0fs:auto_generated.address_a[3]
address_a[4] => altsyncram_0fs:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_0fs:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_0fs:auto_generated.q_a[0]
q_a[1] <= altsyncram_0fs:auto_generated.q_a[1]
q_a[2] <= altsyncram_0fs:auto_generated.q_a[2]
q_a[3] <= altsyncram_0fs:auto_generated.q_a[3]
q_a[4] <= altsyncram_0fs:auto_generated.q_a[4]
q_a[5] <= altsyncram_0fs:auto_generated.q_a[5]
q_a[6] <= altsyncram_0fs:auto_generated.q_a[6]
q_a[7] <= altsyncram_0fs:auto_generated.q_a[7]
q_a[8] <= altsyncram_0fs:auto_generated.q_a[8]
q_a[9] <= altsyncram_0fs:auto_generated.q_a[9]
q_a[10] <= altsyncram_0fs:auto_generated.q_a[10]
q_a[11] <= altsyncram_0fs:auto_generated.q_a[11]
q_a[12] <= altsyncram_0fs:auto_generated.q_a[12]
q_a[13] <= altsyncram_0fs:auto_generated.q_a[13]
q_a[14] <= altsyncram_0fs:auto_generated.q_a[14]
q_a[15] <= altsyncram_0fs:auto_generated.q_a[15]
q_b[0] <= <GND>


|step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated
address_a[0] => altsyncram_s6a2:altsyncram1.address_a[0]
address_a[1] => altsyncram_s6a2:altsyncram1.address_a[1]
address_a[2] => altsyncram_s6a2:altsyncram1.address_a[2]
address_a[3] => altsyncram_s6a2:altsyncram1.address_a[3]
address_a[4] => altsyncram_s6a2:altsyncram1.address_a[4]
clock0 => altsyncram_s6a2:altsyncram1.clock0
q_a[0] <= altsyncram_s6a2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_s6a2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_s6a2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_s6a2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_s6a2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_s6a2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_s6a2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_s6a2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_s6a2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_s6a2:altsyncram1.q_a[9]
q_a[10] <= altsyncram_s6a2:altsyncram1.q_a[10]
q_a[11] <= altsyncram_s6a2:altsyncram1.q_a[11]
q_a[12] <= altsyncram_s6a2:altsyncram1.q_a[12]
q_a[13] <= altsyncram_s6a2:altsyncram1.q_a[13]
q_a[14] <= altsyncram_s6a2:altsyncram1.q_a[14]
q_a[15] <= altsyncram_s6a2:altsyncram1.q_a[15]


|step_a|rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[0] => ram_block3a10.PORTAADDR
address_a[0] => ram_block3a11.PORTAADDR
address_a[0] => ram_block3a12.PORTAADDR
address_a[0] => ram_block3a13.PORTAADDR
address_a[0] => ram_block3a14.PORTAADDR
address_a[0] => ram_block3a15.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[1] => ram_block3a10.PORTAADDR1
address_a[1] => ram_block3a11.PORTAADDR1
address_a[1] => ram_block3a12.PORTAADDR1
address_a[1] => ram_block3a13.PORTAADDR1
address_a[1] => ram_block3a14.PORTAADDR1
address_a[1] => ram_block3a15.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[2] => ram_block3a10.PORTAADDR2
address_a[2] => ram_block3a11.PORTAADDR2
address_a[2] => ram_block3a12.PORTAADDR2
address_a[2] => ram_block3a13.PORTAADDR2
address_a[2] => ram_block3a14.PORTAADDR2
address_a[2] => ram_block3a15.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[3] => ram_block3a10.PORTAADDR3
address_a[3] => ram_block3a11.PORTAADDR3
address_a[3] => ram_block3a12.PORTAADDR3
address_a[3] => ram_block3a13.PORTAADDR3
address_a[3] => ram_block3a14.PORTAADDR3
address_a[3] => ram_block3a15.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[4] => ram_block3a10.PORTAADDR4
address_a[4] => ram_block3a11.PORTAADDR4
address_a[4] => ram_block3a12.PORTAADDR4
address_a[4] => ram_block3a13.PORTAADDR4
address_a[4] => ram_block3a14.PORTAADDR4
address_a[4] => ram_block3a15.PORTAADDR4
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[0] => ram_block3a10.PORTBADDR
address_b[0] => ram_block3a11.PORTBADDR
address_b[0] => ram_block3a12.PORTBADDR
address_b[0] => ram_block3a13.PORTBADDR
address_b[0] => ram_block3a14.PORTBADDR
address_b[0] => ram_block3a15.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[1] => ram_block3a10.PORTBADDR1
address_b[1] => ram_block3a11.PORTBADDR1
address_b[1] => ram_block3a12.PORTBADDR1
address_b[1] => ram_block3a13.PORTBADDR1
address_b[1] => ram_block3a14.PORTBADDR1
address_b[1] => ram_block3a15.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[2] => ram_block3a10.PORTBADDR2
address_b[2] => ram_block3a11.PORTBADDR2
address_b[2] => ram_block3a12.PORTBADDR2
address_b[2] => ram_block3a13.PORTBADDR2
address_b[2] => ram_block3a14.PORTBADDR2
address_b[2] => ram_block3a15.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[3] => ram_block3a10.PORTBADDR3
address_b[3] => ram_block3a11.PORTBADDR3
address_b[3] => ram_block3a12.PORTBADDR3
address_b[3] => ram_block3a13.PORTBADDR3
address_b[3] => ram_block3a14.PORTBADDR3
address_b[3] => ram_block3a15.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[4] => ram_block3a10.PORTBADDR4
address_b[4] => ram_block3a11.PORTBADDR4
address_b[4] => ram_block3a12.PORTBADDR4
address_b[4] => ram_block3a13.PORTBADDR4
address_b[4] => ram_block3a14.PORTBADDR4
address_b[4] => ram_block3a15.PORTBADDR4
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock0 => ram_block3a8.CLK0
clock0 => ram_block3a9.CLK0
clock0 => ram_block3a10.CLK0
clock0 => ram_block3a11.CLK0
clock0 => ram_block3a12.CLK0
clock0 => ram_block3a13.CLK0
clock0 => ram_block3a14.CLK0
clock0 => ram_block3a15.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
clock1 => ram_block3a8.CLK1
clock1 => ram_block3a9.CLK1
clock1 => ram_block3a10.CLK1
clock1 => ram_block3a11.CLK1
clock1 => ram_block3a12.CLK1
clock1 => ram_block3a13.CLK1
clock1 => ram_block3a14.CLK1
clock1 => ram_block3a15.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
data_b[8] => ram_block3a8.PORTBDATAIN
data_b[9] => ram_block3a9.PORTBDATAIN
data_b[10] => ram_block3a10.PORTBDATAIN
data_b[11] => ram_block3a11.PORTBDATAIN
data_b[12] => ram_block3a12.PORTBDATAIN
data_b[13] => ram_block3a13.PORTBDATAIN
data_b[14] => ram_block3a14.PORTBDATAIN
data_b[15] => ram_block3a15.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_a[8] <= ram_block3a8.PORTADATAOUT
q_a[9] <= ram_block3a9.PORTADATAOUT
q_a[10] <= ram_block3a10.PORTADATAOUT
q_a[11] <= ram_block3a11.PORTADATAOUT
q_a[12] <= ram_block3a12.PORTADATAOUT
q_a[13] <= ram_block3a13.PORTADATAOUT
q_a[14] <= ram_block3a14.PORTADATAOUT
q_a[15] <= ram_block3a15.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
q_b[8] <= ram_block3a8.PORTBDATAOUT
q_b[9] <= ram_block3a9.PORTBDATAOUT
q_b[10] <= ram_block3a10.PORTBDATAOUT
q_b[11] <= ram_block3a11.PORTBDATAOUT
q_b[12] <= ram_block3a12.PORTBDATAOUT
q_b[13] <= ram_block3a13.PORTBDATAOUT
q_b[14] <= ram_block3a14.PORTBDATAOUT
q_b[15] <= ram_block3a15.PORTBDATAOUT