step_a.hier_info

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

|step_a
Z <= 21mux:65.Y
D_STP => DECD:136.CLK
clk5 => CNT5:132.CLK
clk5 => inst5.CLK
clk5 => inst6.CLK
clk5 => CNT8:83.CLK
Z_F => 21mux:65.S
Z_F => 21mux:66.S
F <= 21mux:66.Y
COUT <= FREQTEST:121.CCOUT
clk0 => inst8.CLK
clk0 => DEC2:125.CLK
clk0 => CNT24:127.CLK
clk0 => rom3:inst.inclock
CNTT => inst5.DATAIN
cntout <= inst7.DB_MAX_OUTPUT_PORT_TYPE
D[0] <= FREQTEST:121.DOUT[0]
D[1] <= FREQTEST:121.DOUT[1]
D[2] <= FREQTEST:121.DOUT[2]
D[3] <= FREQTEST:121.DOUT[3]
D[4] <= FREQTEST:121.DOUT[4]
D[5] <= FREQTEST:121.DOUT[5]
D[6] <= FREQTEST:121.DOUT[6]
D[7] <= FREQTEST:121.DOUT[7]
D[8] <= FREQTEST:121.DOUT[8]
D[9] <= FREQTEST:121.DOUT[9]
D[10] <= FREQTEST:121.DOUT[10]
D[11] <= FREQTEST:121.DOUT[11]
D[12] <= FREQTEST:121.DOUT[12]
D[13] <= FREQTEST:121.DOUT[13]
D[14] <= FREQTEST:121.DOUT[14]
D[15] <= FREQTEST:121.DOUT[15]
DLED[0] <= DECD:136.DSPY[0]
DLED[1] <= DECD:136.DSPY[1]
Y[0] <= BUSMUX:41.result[0]
Y[1] <= BUSMUX:41.result[1]
Y[2] <= BUSMUX:41.result[2]
Y[3] <= BUSMUX:41.result[3]
S => BUSMUX:41.sel
u_d => CNT24:127.U_D


|step_a|21mux:65
Y <= 5.DB_MAX_OUTPUT_PORT_TYPE
A => 6.IN0
S => 6.IN1
S => 7.IN1
B => 8.IN0


|step_a|cmp3:131
agb <= LPM_COMPARE:1.agb
a[0] => LPM_COMPARE:1.dataa[0]
a[1] => LPM_COMPARE:1.dataa[1]
a[2] => LPM_COMPARE:1.dataa[2]
a[3] => LPM_COMPARE:1.dataa[3]
b[0] => LPM_COMPARE:1.datab[0]
b[1] => LPM_COMPARE:1.datab[1]
b[2] => LPM_COMPARE:1.datab[2]
b[3] => LPM_COMPARE:1.datab[3]


|step_a|cmp3:131|LPM_COMPARE:1
dataa[0] => comptree:comparator.dataa[0]
dataa[1] => comptree:comparator.dataa[1]
dataa[2] => comptree:comparator.dataa[2]
dataa[3] => comptree:comparator.dataa[3]
datab[0] => comptree:comparator.datab[0]
datab[1] => comptree:comparator.datab[1]
datab[2] => comptree:comparator.datab[2]
datab[3] => comptree:comparator.datab[3]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_xnode.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_xnode.DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:131|LPM_COMPARE:1|comptree:comparator
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
dataa[2] => cmpchain:cmp_end.dataa[2]
dataa[3] => cmpchain:cmp_end.dataa[3]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
datab[2] => cmpchain:cmp_end.datab[2]
datab[3] => cmpchain:cmp_end.datab[3]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= <GND>
agb <= cmpchain:cmp_end.agb


|step_a|cmp3:131|LPM_COMPARE:1|comptree:comparator|cmpchain:cmp_end
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:131|LPM_COMPARE:1|altshift:aeb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|step_a|cmp3:131|LPM_COMPARE:1|altshift:agb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|step_a|DECD:136
CLK => CQ[0].CLK
CLK => CQ[1].CLK
DSPY[0] <= CQ[0].DB_MAX_OUTPUT_PORT_TYPE
DSPY[1] <= CQ[1].DB_MAX_OUTPUT_PORT_TYPE
D[0] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
D[1] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
D[2] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
D[3] <= CQ[1].DB_MAX_OUTPUT_PORT_TYPE


|step_a|CNT5:132
CLK => CQI[3].CLK
CLK => CQI[2].CLK
CLK => CQI[1].CLK
CLK => CQI[0].CLK
CLK => CQI[4].CLK
AA[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
AA[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
AA[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
AA[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE


|step_a|21mux:66
Y <= 5.DB_MAX_OUTPUT_PORT_TYPE
A => 6.IN0
S => 6.IN1
S => 7.IN1
B => 8.IN0


|step_a|FREQTEST:121
CLK => TESTCTL:U1.CLK
FSIN => CNT:U3.CLOCK
CCOUT <= CNT:U3.COUT
DOUT[0] <= REG:U2.Q[0]
DOUT[1] <= REG:U2.Q[1]
DOUT[2] <= REG:U2.Q[2]
DOUT[3] <= REG:U2.Q[3]
DOUT[4] <= REG:U2.Q[4]
DOUT[5] <= REG:U2.Q[5]
DOUT[6] <= REG:U2.Q[6]
DOUT[7] <= REG:U2.Q[7]
DOUT[8] <= REG:U2.Q[8]
DOUT[9] <= REG:U2.Q[9]
DOUT[10] <= REG:U2.Q[10]
DOUT[11] <= REG:U2.Q[11]
DOUT[12] <= REG:U2.Q[12]
DOUT[13] <= REG:U2.Q[13]
DOUT[14] <= REG:U2.Q[14]
DOUT[15] <= REG:U2.Q[15]


|step_a|FREQTEST:121|TESTCTL:U1
CLK => Div2CLK.CLK
CLK => process1~0.IN1
TSTEN <= Div2CLK.DB_MAX_OUTPUT_PORT_TYPE
CLR_CNT <= process1~0.DB_MAX_OUTPUT_PORT_TYPE
Load <= Div2CLK.DB_MAX_OUTPUT_PORT_TYPE


|step_a|FREQTEST:121|REG:U2
clock => lpm_ff:lpm_ff_component.clock
data[0] => lpm_ff:lpm_ff_component.data[0]
data[1] => lpm_ff:lpm_ff_component.data[1]
data[2] => lpm_ff:lpm_ff_component.data[2]
data[3] => lpm_ff:lpm_ff_component.data[3]
data[4] => lpm_ff:lpm_ff_component.data[4]
data[5] => lpm_ff:lpm_ff_component.data[5]
data[6] => lpm_ff:lpm_ff_component.data[6]
data[7] => lpm_ff:lpm_ff_component.data[7]
data[8] => lpm_ff:lpm_ff_component.data[8]
data[9] => lpm_ff:lpm_ff_component.data[9]
data[10] => lpm_ff:lpm_ff_component.data[10]
data[11] => lpm_ff:lpm_ff_component.data[11]
data[12] => lpm_ff:lpm_ff_component.data[12]
data[13] => lpm_ff:lpm_ff_component.data[13]
data[14] => lpm_ff:lpm_ff_component.data[14]
data[15] => lpm_ff:lpm_ff_component.data[15]
q[0] <= lpm_ff:lpm_ff_component.q[0]
q[1] <= lpm_ff:lpm_ff_component.q[1]
q[2] <= lpm_ff:lpm_ff_component.q[2]
q[3] <= lpm_ff:lpm_ff_component.q[3]
q[4] <= lpm_ff:lpm_ff_component.q[4]
q[5] <= lpm_ff:lpm_ff_component.q[5]
q[6] <= lpm_ff:lpm_ff_component.q[6]
q[7] <= lpm_ff:lpm_ff_component.q[7]
q[8] <= lpm_ff:lpm_ff_component.q[8]
q[9] <= lpm_ff:lpm_ff_component.q[9]
q[10] <= lpm_ff:lpm_ff_component.q[10]
q[11] <= lpm_ff:lpm_ff_component.q[11]
q[12] <= lpm_ff:lpm_ff_component.q[12]
q[13] <= lpm_ff:lpm_ff_component.q[13]
q[14] <= lpm_ff:lpm_ff_component.q[14]
q[15] <= lpm_ff:lpm_ff_component.q[15]


|step_a|FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
data[1] => dffs[1].DATAIN
data[2] => dffs[2].DATAIN
data[3] => dffs[3].DATAIN
data[4] => dffs[4].DATAIN
data[5] => dffs[5].DATAIN
data[6] => dffs[6].DATAIN
data[7] => dffs[7].DATAIN
data[8] => dffs[8].DATAIN
data[9] => dffs[9].DATAIN
data[10] => dffs[10].DATAIN
data[11] => dffs[11].DATAIN
data[12] => dffs[12].DATAIN
data[13] => dffs[13].DATAIN
data[14] => dffs[14].DATAIN
data[15] => dffs[15].DATAIN
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE


|step_a|FREQTEST:121|CNT:U3
clock => lpm_counter:lpm_counter_component.clock
clk_en => lpm_counter:lpm_counter_component.clk_en
aclr => lpm_counter:lpm_counter_component.aclr
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]
q[12] <= lpm_counter:lpm_counter_component.q[12]
q[13] <= lpm_counter:lpm_counter_component.q[13]
q[14] <= lpm_counter:lpm_counter_component.q[14]
q[15] <= lpm_counter:lpm_counter_component.q[15]
cout <= lpm_counter:lpm_counter_component.cout


|step_a|FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component
clock => cntr_8f8:auto_generated.clock
clk_en => cntr_8f8:auto_generated.clk_en
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => cntr_8f8:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_8f8:auto_generated.q[0]
q[1] <= cntr_8f8:auto_generated.q[1]
q[2] <= cntr_8f8:auto_generated.q[2]
q[3] <= cntr_8f8:auto_generated.q[3]
q[4] <= cntr_8f8:auto_generated.q[4]
q[5] <= cntr_8f8:auto_generated.q[5]
q[6] <= cntr_8f8:auto_generated.q[6]
q[7] <= cntr_8f8:auto_generated.q[7]
q[8] <= cntr_8f8:auto_generated.q[8]
q[9] <= cntr_8f8:auto_generated.q[9]
q[10] <= cntr_8f8:auto_generated.q[10]
q[11] <= cntr_8f8:auto_generated.q[11]
q[12] <= cntr_8f8:auto_generated.q[12]
q[13] <= cntr_8f8:auto_generated.q[13]
q[14] <= cntr_8f8:auto_generated.q[14]
q[15] <= cntr_8f8:auto_generated.q[15]
cout <= cntr_8f8:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|step_a|FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component|cntr_8f8:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
aclr => counter_cella13.ACLR
aclr => counter_cella14.ACLR
aclr => counter_cella15.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clk_en => counter_cella8.ENA
clk_en => counter_cella9.ENA
clk_en => counter_cella10.ENA
clk_en => counter_cella11.ENA
clk_en => counter_cella12.ENA
clk_en => counter_cella13.ENA
clk_en => counter_cella14.ENA
clk_en => counter_cella15.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT


|step_a|BUSMUX:41
dataa[0] => lpm_mux:$00000.data[0][0]
dataa[1] => lpm_mux:$00000.data[0][1]
dataa[2] => lpm_mux:$00000.data[0][2]
dataa[3] => lpm_mux:$00000.data[0][3]
datab[0] => lpm_mux:$00000.data[1][0]
datab[1] => lpm_mux:$00000.data[1][1]
datab[2] => lpm_mux:$00000.data[1][2]
datab[3] => lpm_mux:$00000.data[1][3]
sel => lpm_mux:$00000.sel[0]
result[0] <= lpm_mux:$00000.result[0]
result[1] <= lpm_mux:$00000.result[1]
result[2] <= lpm_mux:$00000.result[2]
result[3] <= lpm_mux:$00000.result[3]


|step_a|BUSMUX:41|lpm_mux:$00000
data[0][0] => mux_6fc:auto_generated.data[0]
data[0][1] => mux_6fc:auto_generated.data[1]
data[0][2] => mux_6fc:auto_generated.data[2]
data[0][3] => mux_6fc:auto_generated.data[3]
data[1][0] => mux_6fc:auto_generated.data[4]
data[1][1] => mux_6fc:auto_generated.data[5]