step_a.fit.qmsg

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 8 14 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  14 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 7 21 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 7 total pin(s) used --  21 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 7 23 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 7 total pin(s) used --  23 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 16 12 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 16 total pin(s) used --  12 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.756 ns memory register " "Info: Estimated most critical path is memory to register delay of 5.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a3~portb_address_reg0 1 MEM M4K_X13_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a3~portb_address_reg0'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a3~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 142 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|q_b\[3\] 2 MEM M4K_X13_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|q_b\[3\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "4.317 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a3~portb_address_reg0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[3] } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.738 ns) 5.756 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[3\] 3 REG LAB_X18_Y9 2 " "Info: 3: + IC(0.701 ns) + CELL(0.738 ns) = 5.756 ns; Loc. = LAB_X18_Y9; Fanout = 2; REG Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[3\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.439 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[3] rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] } "NODE_NAME" } "" } } { "sld_mod_ram_rom.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_mod_ram_rom.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.055 ns 87.82 % " "Info: Total cell delay = 5.055 ns ( 87.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.701 ns 12.18 % " "Info: Total interconnect delay = 0.701 ns ( 12.18 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "5.756 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a3~portb_address_reg0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|q_b[3] rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Info: Fitter placement operations ending: elapsed time is 00:00:06" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 7 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 7%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:moto\|reset_all " "Info: Node sld_signaltap:moto\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:moto\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node sld_signaltap:moto\|bypass_reg_out -- routed using non-global resources" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { sld_signaltap:moto|bypass_reg_out } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:moto\|bypass_reg_out" } } } } { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { sld_signaltap:moto|bypass_reg_out } "NODE_NAME" } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { sld_signaltap:moto|reset_all } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:moto\|reset_all" } } } } { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { sld_signaltap:moto|reset_all } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 11 21:43:47 2005 " "Info: Processing ended: Tue Oct 11 21:43:47 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0}  } {  } 0}