step_a.fit.qmsg

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 11 21:43:27 2005 " "Info: Processing started: Tue Oct 11 21:43:27 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off STEP_A -c step_a " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off STEP_A -c step_a" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "step_a EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"step_a\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 37 " "Info: No exact pin location assignment(s) for 5 pins of 37 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "COUT " "Info: Pin COUT not assigned to an exact location on the device" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 752 672 848 768 "COUT" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "COUT" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { COUT } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { COUT } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk5 Global clock in PIN 16 " "Info: Automatically promoted signal \"clk5\" to use Global clock in PIN 16" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 280 120 288 296 "clk5" "" } { 272 288 392 288 "clk5" "" } { 1056 240 384 1072 "clk5" "" } { 584 136 184 600 "clk5" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk0 Global clock in PIN 93 " "Info: Automatically promoted some destinations of signal \"clk0\" to use Global clock in PIN 93" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:moto\|acq_trigger_in_reg\[6\] " "Info: Destination \"sld_signaltap:moto\|acq_trigger_in_reg\[6\]\" may be non-global or may not use global clock" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQTEST:121\|TESTCTL:U1\|TSTEN Global clock " "Info: Automatically promoted some destinations of signal \"FREQTEST:121\|TESTCTL:U1\|TSTEN\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella15 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella15\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|TESTCTL:U1\|TSTEN " "Info: Destination \"FREQTEST:121\|TESTCTL:U1\|TSTEN\" may be non-global or may not use global clock" {  } { { "testctl.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/testctl.vhd" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella14 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella14\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella13 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella13\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella12 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella12\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella11 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella11\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella10 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella10\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella9 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella9\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella8 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella8\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella7 " "Info: Destination \"FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella7\" may be non-global or may not use global clock" {  } { { "db/cntr_8f8.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_8f8.tdf" 174 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "testctl.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/testctl.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "inst7 Global clock " "Info: Automatically promoted some destinations of signal \"inst7\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cntout " "Info: Destination \"cntout\" may be non-global or may not use global clock" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 848 568 744 864 "cntout" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:moto\|acq_trigger_in_reg\[7\] " "Info: Destination \"sld_signaltap:moto\|acq_trigger_in_reg\[7\]\" may be non-global or may not use global clock" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 952 680 744 1000 "inst7" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "D_STP Global clock " "Info: Automatically promoted signal \"D_STP\" to use Global clock" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "D_STP " "Info: Pin \"D_STP\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D_STP" } } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { D_STP } "NODE_NAME" } "" } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.fld" "" "" { D_STP } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:moto\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:moto\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:moto\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 " "Info: Destination \"sld_signaltap:moto\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29\" may be non-global or may not use global clock" {  } { { "sld_acquisition_buffer.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0}  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0\" to use Global clock" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}