step_a.map.qmsg

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_vt9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_vt9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_vt9 " "Info: Found entity 1: cntr_vt9" {  } { { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5f92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5f92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5f92 " "Info: Found entity 1: altsyncram_5f92" {  } { { "db/altsyncram_5f92.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_5f92.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tt7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_tt7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tt7 " "Info: Found entity 1: cntr_tt7" {  } { { "db/cntr_tt7.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_tt7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ln7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ln7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ln7 " "Info: Found entity 1: cntr_ln7" {  } { { "db/cntr_ln7.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_ln7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "moto " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"moto\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|F acq_trigger_in\[0\] " "Info: Source node \"\|step_a\|F\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "step_a.bdf" "F" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 696 576 752 712 "F" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|F acq_data_in\[0\] " "Info: Source node \"\|step_a\|F\" connects to port \"acq_data_in\[0\]\"" {  } { { "step_a.bdf" "F" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 696 576 752 712 "F" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[0\] acq_trigger_in\[1\] " "Info: Source node \"\|step_a\|Y\[0\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "step_a.bdf" "Y\[0\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[0\] acq_data_in\[1\] " "Info: Source node \"\|step_a\|Y\[0\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "step_a.bdf" "Y\[0\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[1\] acq_trigger_in\[2\] " "Info: Source node \"\|step_a\|Y\[1\]\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "step_a.bdf" "Y\[1\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[1\] acq_data_in\[2\] " "Info: Source node \"\|step_a\|Y\[1\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "step_a.bdf" "Y\[1\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[2\] acq_trigger_in\[3\] " "Info: Source node \"\|step_a\|Y\[2\]\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "step_a.bdf" "Y\[2\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[2\] acq_data_in\[3\] " "Info: Source node \"\|step_a\|Y\[2\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "step_a.bdf" "Y\[2\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[3\] acq_trigger_in\[4\] " "Info: Source node \"\|step_a\|Y\[3\]\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "step_a.bdf" "Y\[3\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Y\[3\] acq_data_in\[4\] " "Info: Source node \"\|step_a\|Y\[3\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "step_a.bdf" "Y\[3\]" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 112 376 552 128 "Y\[3..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Z acq_trigger_in\[5\] " "Info: Source node \"\|step_a\|Z\" connects to port \"acq_trigger_in\[5\]\"" {  } { { "step_a.bdf" "Z" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 672 576 752 688 "Z" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|Z acq_data_in\[5\] " "Info: Source node \"\|step_a\|Z\" connects to port \"acq_data_in\[5\]\"" {  } { { "step_a.bdf" "Z" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 672 576 752 688 "Z" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|clk0 acq_trigger_in\[6\] " "Info: Source node \"\|step_a\|clk0\" connects to port \"acq_trigger_in\[6\]\"" {  } { { "step_a.bdf" "clk0" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|clk0 acq_data_in\[6\] " "Info: Source node \"\|step_a\|clk0\" connects to port \"acq_data_in\[6\]\"" {  } { { "step_a.bdf" "clk0" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|clk0 trigger_in " "Info: Source node \"\|step_a\|clk0\" connects to port \"trigger_in\"" {  } { { "step_a.bdf" "clk0" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|clk5 acq_clk " "Info: Source node \"\|step_a\|clk5\" connects to port \"acq_clk\"" {  } { { "step_a.bdf" "clk5" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 280 120 288 296 "clk5" "" } { 272 288 392 288 "clk5" "" } { 1056 240 384 1072 "clk5" "" } { 584 136 184 600 "clk5" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|cntout acq_trigger_in\[7\] " "Info: Source node \"\|step_a\|cntout\" connects to port \"acq_trigger_in\[7\]\"" {  } { { "step_a.bdf" "cntout" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 848 568 744 864 "cntout" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|step_a\|cntout acq_data_in\[7\] " "Info: Source node \"\|step_a\|cntout\" connects to port \"acq_data_in\[7\]\"" {  } { { "step_a.bdf" "cntout" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 848 568 744 864 "cntout" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT24:127\|CQI\[0\] inst8 " "Info: Duplicate register \"CNT24:127\|CQI\[0\]\" merged to single register \"inst8\"" {  } { { "cnt24.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt24.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "Dec2:125\|CQ\[0\] inst8 " "Info: Duplicate register \"Dec2:125\|CQ\[0\]\" merged to single register \"inst8\", power-up level changed" {  } { { "dec2.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/dec2.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT5:132\|CQI\[0\] CNT8:83\|CQI\[0\] " "Info: Duplicate register \"CNT5:132\|CQI\[0\]\" merged to single register \"CNT8:83\|CQI\[0\]\"" {  } { { "cnt5.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt5.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT5:132\|CQI\[1\] CNT8:83\|CQI\[1\] " "Info: Duplicate register \"CNT5:132\|CQI\[1\]\" merged to single register \"CNT8:83\|CQI\[1\]\"" {  } { { "cnt5.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt5.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT5:132\|CQI\[2\] CNT8:83\|CQI\[2\] " "Info: Duplicate register \"CNT5:132\|CQI\[2\]\" merged to single register \"CNT8:83\|CQI\[2\]\"" {  } { { "cnt5.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt5.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT5:132\|CQI\[3\] CNT8:83\|CQI\[3\] " "Info: Duplicate register \"CNT5:132\|CQI\[3\]\" merged to single register \"CNT8:83\|CQI\[3\]\"" {  } { { "cnt5.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt5.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CNT5:132\|CQI\[4\] CNT8:83\|CQI\[4\] " "Info: Duplicate register \"CNT5:132\|CQI\[4\]\" merged to single register \"CNT8:83\|CQI\[4\]\"" {  } { { "cnt5.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/cnt5.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "9 " "Info: Ignored 9 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[7\] sld_signaltap:moto\|acq_trigger_in_reg\[7\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[7\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[7\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[7\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[7\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[0\] sld_signaltap:moto\|acq_trigger_in_reg\[0\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[0\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[0\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[0\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[0\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[1\] sld_signaltap:moto\|acq_trigger_in_reg\[1\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[1\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[1\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[1\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[1\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[2\] sld_signaltap:moto\|acq_trigger_in_reg\[2\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[2\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[2\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[2\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[2\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[3\] sld_signaltap:moto\|acq_trigger_in_reg\[3\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[3\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[3\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[3\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[3\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[4\] sld_signaltap:moto\|acq_trigger_in_reg\[4\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[4\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[4\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[4\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[4\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|trigger_in_reg sld_signaltap:moto\|acq_trigger_in_reg\[6\] " "Info: Duplicate register \"sld_signaltap:moto\|trigger_in_reg\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[6\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 438 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[6\] sld_signaltap:moto\|acq_trigger_in_reg\[6\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[6\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[6\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|sld_ela_control:ela_control\|sld_mbpmg:\\trigger_in_trigger_module_enabled_gen:trigger_in_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_mbpmg:\\trigger_in_trigger_module_enabled_gen:trigger_in_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff\"" {  } { { "sld_mbpmg.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[6\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[6\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_reg\[5\] sld_signaltap:moto\|acq_trigger_in_reg\[5\] " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_reg\[5\]\" merged to single register \"sld_signaltap:moto\|acq_trigger_in_reg\[5\]\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[5\] sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:moto\|acq_data_in_pipe_reg\[1\]\[5\]\" merged to single register \"sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "IFTM_CARRY_SINGLE_TO_DOUBLE" "15 " "Info: Converted 15 single input CARRY primitives to CARRY_SUM primitives" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "585 " "Info: Implemented 585 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "27 " "Info: Implemented 27 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "523 " "Info: Implemented 523 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "24 " "Info: Implemented 24 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 11 21:43:25 2005 " "Info: Processing ended: Tue Oct 11 21:43:25 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Info: Elapsed time: 00:00:26" {  } {  } 0}  } {  } 0}