step_a.tan.qmsg

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "D_STP register register DECD:136\|CQ\[0\] DECD:136\|CQ\[1\] 275.03 MHz Internal " "Info: Clock \"D_STP\" Internal fmax is restricted to 275.03 MHz between source register \"DECD:136\|CQ\[0\]\" and destination register \"DECD:136\|CQ\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.461 ns + Longest register register " "Info: + Longest register to register delay is 1.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DECD:136\|CQ\[0\] 1 REG LC_X16_Y11_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N9; Fanout = 5; REG Node = 'DECD:136\|CQ\[0\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { DECD:136|CQ[0] } "NODE_NAME" } "" } } { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.867 ns) 1.461 ns DECD:136\|CQ\[1\] 2 REG LC_X16_Y11_N6 4 " "Info: 2: + IC(0.594 ns) + CELL(0.867 ns) = 1.461 ns; Loc. = LC_X16_Y11_N6; Fanout = 4; REG Node = 'DECD:136\|CQ\[1\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.461 ns" { DECD:136|CQ[0] DECD:136|CQ[1] } "NODE_NAME" } "" } } { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.867 ns 59.34 % " "Info: Total cell delay = 0.867 ns ( 59.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 40.66 % " "Info: Total interconnect delay = 0.594 ns ( 40.66 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.461 ns" { DECD:136|CQ[0] DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.461 ns" { DECD:136|CQ[0] DECD:136|CQ[1] } { 0.000ns 0.594ns } { 0.000ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "D_STP destination 7.344 ns + Shortest register " "Info: + Shortest clock path from clock \"D_STP\" to destination register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D_STP 1 CLK PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'D_STP'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { D_STP } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.164 ns) + CELL(0.711 ns) 7.344 ns DECD:136\|CQ\[1\] 2 REG LC_X16_Y11_N6 4 " "Info: 2: + IC(5.164 ns) + CELL(0.711 ns) = 7.344 ns; Loc. = LC_X16_Y11_N6; Fanout = 4; REG Node = 'DECD:136\|CQ\[1\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "5.875 ns" { D_STP DECD:136|CQ[1] } "NODE_NAME" } "" } } { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 29.68 % " "Info: Total cell delay = 2.180 ns ( 29.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.164 ns 70.32 % " "Info: Total interconnect delay = 5.164 ns ( 70.32 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[1] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "D_STP source 7.344 ns - Longest register " "Info: - Longest clock path from clock \"D_STP\" to source register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D_STP 1 CLK PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'D_STP'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { D_STP } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.164 ns) + CELL(0.711 ns) 7.344 ns DECD:136\|CQ\[0\] 2 REG LC_X16_Y11_N9 5 " "Info: 2: + IC(5.164 ns) + CELL(0.711 ns) = 7.344 ns; Loc. = LC_X16_Y11_N9; Fanout = 5; REG Node = 'DECD:136\|CQ\[0\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "5.875 ns" { D_STP DECD:136|CQ[0] } "NODE_NAME" } "" } } { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 29.68 % " "Info: Total cell delay = 2.180 ns ( 29.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.164 ns 70.32 % " "Info: Total interconnect delay = 5.164 ns ( 70.32 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[0] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[1] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[0] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.461 ns" { DECD:136|CQ[0] DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.461 ns" { DECD:136|CQ[0] DECD:136|CQ[1] } { 0.000ns 0.594ns } { 0.000ns 0.867ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[1] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "7.344 ns" { D_STP DECD:136|CQ[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.344 ns" { D_STP D_STP~out0 DECD:136|CQ[0] } { 0.000ns 0.000ns 5.164ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { DECD:136|CQ[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { DECD:136|CQ[1] } {  } {  } } } { "decd.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/decd.vhd" 10 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 memory rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15 memory rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk0\" has Internal fmax of 197.01 MHz between source memory \"rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15\" and destination memory \"rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15 1 MEM M4K_X13_Y9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y9; Fanout = 2; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15 2 MEM M4K_X13_Y9 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y9; Fanout = 0; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "4.319 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "4.319 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.778 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk0\" to destination memory is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_93 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 45; CLK Node = 'clk0'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { clk0 } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.708 ns) 2.778 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15 2 MEM M4K_X13_Y9 0 " "Info: 2: + IC(0.601 ns) + CELL(0.708 ns) = 2.778 ns; Loc. = M4K_X13_Y9; Fanout = 0; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_memory_reg15'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.309 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.37 % " "Info: Total cell delay = 2.177 ns ( 78.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.63 % " "Info: Total interconnect delay = 0.601 ns ( 21.63 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.778 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.778 ns" { clk0 clk0~out0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.792 ns - Longest memory " "Info: - Longest clock path from clock \"clk0\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_93 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 45; CLK Node = 'clk0'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { clk0 } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 320 176 344 336 "clk0" "" } { 864 48 136 880 "clk0" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15 2 MEM M4K_X13_Y9 2 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y9; Fanout = 2; MEM Node = 'rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|altsyncram_s6a2:altsyncram1\|ram_block3a15~porta_datain_reg15'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.323 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } "NODE_NAME" } "" } } { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.47 % " "Info: Total cell delay = 2.191 ns ( 78.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.53 % " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.792 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.792 ns" { clk0 clk0~out0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.778 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.778 ns" { clk0 clk0~out0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.792 ns" { clk0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.792 ns" { clk0 clk0~out0 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_s6a2.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_s6a2.tdf" 526 2 0 } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "4.319 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg15 rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg15 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a