step_a.tan.qmsg

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "inst8 " "Info: Detected ripple clock \"inst8\" as buffer" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 840 136 200 920 "inst8" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst8" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "inst9 " "Info: Detected ripple clock \"inst9\" as buffer" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 840 272 336 920 "inst9" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst9" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "FREQTEST:121\|TESTCTL:U1\|TSTEN " "Info: Detected ripple clock \"FREQTEST:121\|TESTCTL:U1\|TSTEN\" as buffer" {  } { { "testctl.vhd" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/testctl.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FREQTEST:121\|TESTCTL:U1\|TSTEN" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "inst6 " "Info: Detected ripple clock \"inst6\" as buffer" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 960 520 584 1040 "inst6" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst6" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "inst7 " "Info: Detected gated clock \"inst7\" as buffer" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 952 680 744 1000 "inst7" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst7" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "inst5 " "Info: Detected ripple clock \"inst5\" as buffer" {  } { { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 960 408 472 1040 "inst5" "" } } } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst5" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk5 register sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\] memory sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1 173.19 MHz 5.774 ns Internal " "Info: Clock \"clk5\" has Internal fmax of 173.19 MHz between source register \"sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\]\" and destination memory \"sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1\" (period= 5.774 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.481 ns + Longest register memory " "Info: + Longest register to memory delay is 5.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\] 1 REG LC_X12_Y5_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y5_N6; Fanout = 9; REG Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 134 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella2~COUTCOUT1_3 2 COMB LC_X12_Y5_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X12_Y5_N6; Fanout = 2; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella2~COUTCOUT1_3'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.098 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 49 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella3~COUTCOUT1_3 3 COMB LC_X12_Y5_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X12_Y5_N7; Fanout = 2; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella3~COUTCOUT1_3'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.080 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 57 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella4~COUTCOUT1_3 4 COMB LC_X12_Y5_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X12_Y5_N8; Fanout = 2; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella4~COUTCOUT1_3'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.080 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 65 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella5~COUT 5 COMB LC_X12_Y5_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X12_Y5_N9; Fanout = 6; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella5~COUT'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.258 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 73 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella10~COUT 6 COMB LC_X12_Y4_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X12_Y4_N4; Fanout = 1; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|counter_cella10~COUT'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.136 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 113 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.273 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|cout 7 COMB LC_X12_Y4_N5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.273 ns; Loc. = LC_X12_Y4_N5; Fanout = 3; COMB Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|cout'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.621 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 167 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.569 ns sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~110 8 COMB LC_X12_Y4_N6 3 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 2.569 ns; Loc. = LC_X12_Y4_N6; Fanout = 3; COMB Node = 'sld_signaltap:moto\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~110'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.296 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "e:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.865 ns sld_signaltap:moto\|sld_ela_control:ela_control\|buffer_write_ena_int~42 9 COMB LC_X12_Y4_N7 52 " "Info: 9: + IC(0.182 ns) + CELL(0.114 ns) = 2.865 ns; Loc. = LC_X12_Y4_N7; Fanout = 52; COMB Node = 'sld_signaltap:moto\|sld_ela_control:ela_control\|buffer_write_ena_int~42'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "0.296 ns" { sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.965 ns) 5.481 ns sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1 10 MEM M4K_X13_Y5 2 " "Info: 10: + IC(1.651 ns) + CELL(0.965 ns) = 5.481 ns; Loc. = M4K_X13_Y5; Fanout = 2; MEM Node = 'sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.616 ns" { sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_5f92.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_5f92.tdf" 226 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.943 ns 53.69 % " "Info: Total cell delay = 2.943 ns ( 53.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.538 ns 46.31 % " "Info: Total interconnect delay = 2.538 ns ( 46.31 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "5.481 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.481 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.182ns 0.182ns 1.651ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.965ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.024 ns - Smallest " "Info: - Smallest clock skew is 0.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5 destination 2.754 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk5\" to destination memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk5 1 CLK PIN_16 154 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 154; CLK Node = 'clk5'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { clk5 } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 280 120 288 296 "clk5" "" } { 272 288 392 288 "clk5" "" } { 1056 240 384 1072 "clk5" "" } { 584 136 184 600 "clk5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1 2 MEM M4K_X13_Y5 2 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y5; Fanout = 2; MEM Node = 'sld_signaltap:moto\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_5f92:auto_generated\|ram_block1a6~porta_datain_reg1'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.285 ns" { clk5 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_5f92.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_5f92.tdf" 226 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.56 % " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.44 % " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.754 ns" { clk5 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk5 clk5~out0 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5 source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk5\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk5 1 CLK PIN_16 154 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 154; CLK Node = 'clk5'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "" { clk5 } "NODE_NAME" } "" } } { "step_a.bdf" "" { Schematic "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/step_a.bdf" { { 280 120 288 296 "clk5" "" } { 272 288 392 288 "clk5" "" } { 1056 240 384 1072 "clk5" "" } { 584 136 184 600 "clk5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\] 2 REG LC_X12_Y5_N6 9 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X12_Y5_N6; Fanout = 9; REG Node = 'sld_signaltap:moto\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_vt9:auto_generated\|safe_q\[2\]'" {  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "1.261 ns" { clk5 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 134 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.730 ns" { clk5 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk5 clk5~out0 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.754 ns" { clk5 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk5 clk5~out0 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.730 ns" { clk5 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk5 clk5~out0 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_vt9.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/cntr_vt9.tdf" 134 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_5f92.tdf" "" { Text "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/altsyncram_5f92.tdf" 226 2 0 } }  } 0}  } { { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "5.481 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.481 ns" { sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella2~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella3~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella4~COUTCOUT1_3 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella5~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|counter_cella10~COUT sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|cout sld_signaltap:moto|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~110 sld_signaltap:moto|sld_ela_control:ela_control|buffer_write_ena_int~42 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.182ns 0.182ns 1.651ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.965ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.754 ns" { clk5 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { clk5 clk5~out0 sld_signaltap:moto|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5f92:auto_generated|ram_block1a6~porta_datain_reg1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" "" { Report "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/db/STEP_A.quartus_db" { Floorplan "E:/GW48-PK3/EDA新板子/Chpt12_vga_moto/EP1C3_12_1_2_MOTO/" "" "2.730 ns" { clk5 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk5 clk5~out0 sld_signaltap:moto|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_vt9:auto_generated|safe_q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}