step_a.hif

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
11
PARAMETER_DEC
USR
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5f92
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b10
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
clocken1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
wren_a
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_5f92
# case_insensitive
# source_file
db|altsyncram_5f92.tdf
1129038194
6
# storage
db|step_a.(61).cnf
db|step_a.(61).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# end
# entity
sld_offload_buffer_mgr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_acquisition_buffer.vhd
1114012240
4
# storage
db|step_a.(62).cnf
db|step_a.(62).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
buffer_depth
2048
PARAMETER_DEC
USR
mem_address_bits
11
PARAMETER_DEC
USR
data_bits
8
PARAMETER_DEC
USR
data_bit_cntr_bits
3
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|step_a.(63).cnf
db|step_a.(63).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
8
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_tt7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q1
q2
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|..|..|..|altera|quartus50|libraries|megafunctions|cmpconst.inc
1107573980
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
..|..|..|..|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_synch_counter.inc
1107572664
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
cntr_tt7
# case_insensitive
# source_file
db|cntr_tt7.tdf
1129038194
6
# storage
db|step_a.(64).cnf
db|step_a.(64).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|step_a.(65).cnf
db|step_a.(65).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
11
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
2048
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_ln7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q10
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|..|..|..|altera|quartus50|libraries|megafunctions|cmpconst.inc
1107573980
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
..|..|..|..|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_synch_counter.inc
1107572664
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
..|..|..|..|altera|quartus50|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
cntr_ln7
# case_insensitive
# source_file
db|cntr_ln7.tdf
1129038194
6
# storage
db|step_a.(66).cnf
db|step_a.(66).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|step_a.(67).cnf
db|step_a.(67).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data1
data2
data3
data4
data5
data6
data7
enable
load
shiftin
shiftout
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|..|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|step_a.(68).cnf
db|step_a.(68).cnf
# user_parameter {
LPM_WIDTH
23
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|..|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|step_a.(69).cnf
db|step_a.(69).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
32
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|step_a.(70).cnf
db|step_a.(70).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
7
PARAMETER_UNKNOWN
USR
node_info
0001100000000000011011100000000000001000000110000110111000000000
PARAMETER_BIN
USR
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
4
# storage
db|step_a.(71).cnf
db|step_a.(71).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1114012238
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|step_a.(72).cnf
db|step_a.(72).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETE