step_a.hif

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom3.vhd
1106890282
4
# storage
db|step_a.(21).cnf
db|step_a.(21).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rom3:inst
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|step_a.(22).cnf
db|step_a.(22).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
PWM_1.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0fs
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
clock0
q_a0
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
rom3:inst|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_0fs
# case_insensitive
# source_file
db|altsyncram_0fs.tdf
1129038188
6
# storage
db|step_a.(23).cnf
db|step_a.(23).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# hierarchies {
rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated
}
# end
# entity
altsyncram_s6a2
# case_insensitive
# source_file
db|altsyncram_s6a2.tdf
1129038188
6
# storage
db|step_a.(24).cnf
db|step_a.(24).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
}
# memory_file {
PWM_1.mif
1099451084
}
# hierarchies {
rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
4
# storage
db|step_a.(25).cnf
db|step_a.(25).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
16
PARAMETER_UNKNOWN
USR
numwords
32
PARAMETER_UNKNOWN
USR
widthad
5
PARAMETER_UNKNOWN
USR
shift_count_bits
5
PARAMETER_UNKNOWN
USR
cvalue
0000000000000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1919905076
PARAMETER_UNKNOWN
USR
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_mod_ram_rom.vhd
1114012240
}
# hierarchies {
rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1114012236
4
# storage
db|step_a.(26).cnf
db|step_a.(26).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# hierarchies {
rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
}
# end
# entity
CNT8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt8.vhd
1106879212
4
# storage
db|step_a.(27).cnf
db|step_a.(27).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
CNT8:83
}
# end
# entity
sld_signaltap
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_signaltap.vhd
1114012240
4
# storage
db|step_a.(28).cnf
db|step_a.(28).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
402681344
PARAMETER_UNKNOWN
USR
sld_ip_version
3
PARAMETER_DEC
DEF
sld_ip_minor_version
2
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
sld_data_bits
8
PARAMETER_UNKNOWN
USR
sld_trigger_bits
8
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
3
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_DEC
DEF
sld_node_crc_hiword
47858
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
36472
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
11
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
1
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_signaltap.vhd
1114012240
}
# end
# entity
sld_ela_control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114012238
4
# storage
db|step_a.(29).cnf
db|step_a.(29).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_input_width
8
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
trigger_in_enabled
1
PARAMETER_DEC
USR
enable_clk_edge_def
0
PARAMETER_DEC
USR
enable_async_glitch
0
PARAMETER_DEC
USR
enable_sync_normal
1
PARAMETER_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
mem_address_bits
11
PARAMETER_DEC
USR
sample_depth
2048
PARAMETER_DEC
USR
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|step_a.(30).cnf
db|step_a.(30).cnf
# user_parameter {
LPM_WIDTH
20
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
q0
q10
q11
q12
q13
q14
q15
q16
q17
q18
q19
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
shiftout
}
# include_file {
..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
..|..|..|..|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
sld_ela_basic_multi_level_trigger
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|sld_ela_control.vhd
1114012238
4
# storage
db|step_a.(31).cnf
db|step_a.(31).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
data_bits
8
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage