altsyncram_0fs.tdf

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="YES" INIT_FILE="PWM_1.mif" INSTANCE_NAME="rom4" NUMWORDS_A=32 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=5 address_a clock0 q_a
--VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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FUNCTION altsyncram_s6a2 (address_a[4..0], address_b[4..0], clock0, clock1, data_b[15..0], wren_b)
RETURNS ( q_a[15..0], q_b[15..0]);
FUNCTION sld_mod_ram_rom (data_read[15..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[4..0], data_write[15..0], enable_write, tck_usr);

--synthesis_resources = M4K 1 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_0fs
( 
	address_a[4..0]	:	input;
	clock0	:	input;
	q_a[15..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_s6a2;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "0000000000000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 1919905076,
			NUMWORDS = 32,
			SHIFT_COUNT_BITS = 5,
			WIDTH_WORD = 16,
			WIDTHAD = 5
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE