step_a.map.rpt

基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写

Analysis & Synthesis report for step_a
Tue Oct 11 21:43:25 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: cmp3:131|LPM_COMPARE:1
 12. Parameter Settings for User Entity Instance: FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component
 13. Parameter Settings for User Entity Instance: FREQTEST:121|CNT:U3|lpm_counter:lpm_counter_component
 14. Parameter Settings for User Entity Instance: BUSMUX:41
 15. Parameter Settings for User Entity Instance: cmp3:93|LPM_COMPARE:1
 16. Parameter Settings for User Entity Instance: rom3:inst|altsyncram:altsyncram_component
 17. Parameter Settings for User Entity Instance: rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|sld_mod_ram_rom:mgl_prim2
 18. Parameter Settings for User Entity Instance: cmp3:94|LPM_COMPARE:1
 19. Parameter Settings for User Entity Instance: cmp3:95|LPM_COMPARE:1
 20. Parameter Settings for User Entity Instance: cmp3:96|LPM_COMPARE:1
 21. Parameter Settings for Inferred Entity Instance: sld_signaltap:moto
 22. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 23. SignalTap II Logic Analyzer Settings
 24. In-System Memory Content Editor Settings
 25. Analysis & Synthesis Equations
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Oct 11 21:43:25 2005    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; step_a                                   ;
; Top-level Entity Name       ; step_a                                   ;