color.qsf

基于FPGA的VGA彩条显示程序

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		COLOR_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:14:13  JANUARY 29, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE color.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_1 -to MD
set_location_assignment PIN_140 -to VS
set_location_assignment PIN_139 -to HS
set_location_assignment PIN_131 -to R
set_location_assignment PIN_132 -to G
set_location_assignment PIN_134 -to B
set_location_assignment PIN_92 -to CLK

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY COLOR

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 0.0ns

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# -------------------
# start ENTITY(color)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name AUTO_LCELL_INSERTION ON -entity color

# end ENTITY(color)
# -----------------