reserv.vhd

来自「基于ＦＰＧＡ的数字存储示波器」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RESERV IS
    PORT(CLK, KEY1 : IN  STD_LOGIC;
         DA_CLK,AD_CLK : OUT  STD_LOGIC;
        TRAG, DOUT : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 
           ADIN   : IN  STD_LOGIC_VECTOR (7 DOWNTO 0)  );
END;
ARCHITECTURE DACC OF RESERV IS
COMPONENT DPRAM
	PORT (	address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
	  inclock, wren	: IN STD_LOGIC ;
	    	   data	: IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
		        q   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
    SIGNAL    Q1   : STD_LOGIC_VECTOR (9 DOWNTO 0);
    SIGNAL MD0,DIN : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS(CLK)
      BEGIN
        IF rising_edge(CLK) THEN  Q1 <= Q1 + 1;  END IF;
END PROCESS;
process(CLK, ADIN)
begin
 if rising_edge(CLK) then DIN <= ADIN ; end if;
end process;
  DOUT(9 DOWNTO 2)<=MD0; TRAG<=Q1; DOUT(1 DOWNTO 0) <= "00";
  u1 : DPRAM PORT MAP(data=>DIN, wren=>KEY1, address=>Q1, q=>MD0, inclock=>CLK);
DA_CLK<=CLK; AD_CLK<=CLK;
END;