stp1.stp

基于ＦＰＧＡ的数字存储示波器

          <wire connection_status="true" name="DOUT[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[8]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[9]" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <bus link="all" name="ADIN" order="msb_to_lsb" radix="line" state="collapse" type="input pin">
            <net name="ADIN[7]"/>
            <net name="ADIN[6]"/>
            <net name="ADIN[5]"/>
            <net name="ADIN[4]"/>
            <net name="ADIN[3]"/>
            <net name="ADIN[2]"/>
            <net name="ADIN[1]"/>
            <net name="ADIN[0]"/>
          </bus>
          <bus link="all" name="DOUT" order="msb_to_lsb" radix="line" state="collapse" type="output pin">
            <net name="DOUT[9]"/>
            <net name="DOUT[8]"/>
            <net name="DOUT[7]"/>
            <net name="DOUT[6]"/>
            <net name="DOUT[5]"/>
            <net name="DOUT[4]"/>
            <net name="DOUT[3]"/>
            <net name="DOUT[2]"/>
            <net name="DOUT[1]"/>
            <net name="DOUT[0]"/>
          </bus>
        </setup_view>
        <data_view>
          <bus link="all" name="ADIN" order="msb_to_lsb" radix="line" state="collapse" type="input pin">
            <net name="ADIN[7]"/>
            <net name="ADIN[6]"/>
            <net name="ADIN[5]"/>
            <net name="ADIN[4]"/>
            <net name="ADIN[3]"/>
            <net name="ADIN[2]"/>
            <net name="ADIN[1]"/>