mul10.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    10:05:34 04/09/08
-- Design Name:    
-- Module Name:    mul10 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul10 is
		port(
		mul10_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul10_out:out std_logic_vector(12 downto 0)
		);
end mul10;

architecture Behavioral of mul10 is

begin

mul10_out(0)<=mul10_in(3) xor mul10_in(12);
mul10_out(1)<=mul10_in(4) xor mul10_in(12) xor mul10_in(3);
mul10_out(2)<=mul10_in(5) xor mul10_in(4);
mul10_out(3)<=mul10_in(3) xor mul10_in(12) xor mul10_in(6) xor mul10_in(5);
mul10_out(4)<=mul10_in(4) xor mul10_in(6) xor mul10_in(12) xor mul10_in(7) xor mul10_in(3);
mul10_out(5)<=mul10_in(5) xor mul10_in(8) xor mul10_in(4) xor mul10_in(7);
mul10_out(6)<=mul10_in(6) xor mul10_in(8) xor mul10_in(9) xor mul10_in(5);
mul10_out(7)<=mul10_in(7) xor mul10_in(9) xor mul10_in(10) xor mul10_in(6);
mul10_out(8)<=mul10_in(11) xor mul10_in(10) xor mul10_in(8) xor mul10_in(7);
mul10_out(9)<=mul10_in(11) xor mul10_in(9) xor mul10_in(12) xor mul10_in(8);
mul10_out(10)<=mul10_in(12) xor mul10_in(0) xor mul10_in(10) xor mul10_in(9);
mul10_out(11)<=mul10_in(11) xor mul10_in(10) xor mul10_in(1);
mul10_out(12)<=mul10_in(2) xor mul10_in(12) xor mul10_in(11);


end Behavioral;