encode.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    16:10:27 03/20/08
-- Design Name:    
-- Module Name:    encode - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encode is
	port
	(
	in_clk:in std_logic;
	in_rst:in std_logic;
	in_en:in std_logic;
	in_data:in std_logic_vector(7 downto 0);
	out_clk:out std_logic;
	out_en:out std_logic;
	out_data:out std_logic_vector(7 downto 0)
	);
end encode;

architecture Behavioral of encode is

component fifo_left
	port
	(
	clk: IN std_logic;
	sinit: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	rd_en: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic;
	data_count: OUT std_logic_VECTOR(0 downto 0)

	);
end component; 

component serialparallel
	port
	(    
	 	  clock:in std_logic;
	 	  reset:in std_logic;
		  d_in:std_logic_vector(7 downto 0);
		  en_in:in std_logic;		
		  en_out:in std_logic;
		--  d1:out std_logic_vector(135 downto 0);
		  dout:out std_logic_vector(7 downto 0)
	);
	end component;

component controller_encode
	port
	(
	con_clk:in std_logic;
	con_rst:in std_logic;
	con_ready:in std_logic;
	con_read:out std_logic;
	data_sample:out std_logic;
	rem_sample:out std_logic;
	con_output:out std_logic
	);
end component;



signal read:std_logic;
signal out_rem:std_logic;
signal data_mes:std_logic_vector(7 downto 0);
signal data_rem:std_logic_vector(7 downto 0);
--signal d_tmp:std_logic_vector(135 downto 0);
signal read_mes:std_logic;
signal out_rem_m:std_logic;
signal data_sample_all:std_logic;
signal rem_sample_all:std_logic;
signal data_sample_all_m:std_logic;
signal rem_sample_all_m:std_logic;


signal datacount:std_logic_vector(0 downto 0);
signal full,empty:std_logic;

begin

encode_pro:
	serialparallel
	port map
	(
		  clock=>in_clk,
	 	  reset=>in_rst,
		  d_in=>data_mes,
		  en_in=>read_mes,	  
		  en_out=>out_rem_m,	  
	--	  d1=>d_tmp,
		  dout=>data_rem
	);

fifo_pro:
	fifo_left
	port map
	(
	clk=>in_clk,
	sinit=>in_rst,
	din=>in_data,
	wr_en=>in_en,
	rd_en=>read,	 
	dout=>data_mes,
	full=>full,
	empty=>empty,
	data_count=>datacount
	

	);


control_pro:
	controller_encode
	port map
	(
	con_clk=>in_clk,
	con_rst=>in_rst,
	con_ready=>datacount(0),
	con_read=>read,
	data_sample=>data_sample_all,
	rem_sample=>rem_sample_all,
	con_output=>out_rem
	);

out_clk<=in_clk;


main_pro:
		process(in_clk,in_rst)
			begin
		if(in_rst='1')then
		 		out_en<='0';
		     	out_data<=(others=>'0');												
		elsif (in_clk'event and in_clk='1') then
			if(data_sample_all_m='1' and  rem_sample_all_m='0') then
				out_data<=data_mes;
				out_en<='1';
			elsif(rem_sample_all_m='1' and data_sample_all_m='0') then	
				out_data<=data_rem;
				out_en<='1';
		    elsif(rem_sample_all_m='1' and data_sample_all_m='1') then	 
		      out_data<=data_mes;																	 
				out_en<='0';
			 else
			    out_data<=(others=>'0');
				 out_en<='0';
			 end if;
		end if;
		end process;

en_pro:																 
		process(in_clk,in_rst)											
		begin															
		if(in_rst='1')then
		 data_sample_all_m<='0';
		 rem_sample_all_m<='0';	
		 read_mes<='0';
		 out_rem_m<='0';
		elsif(in_clk'event and in_clk='1')then				 
				read_mes<=read;									  
				out_rem_m<=out_rem;
				data_sample_all_m<=data_sample_all;
				rem_sample_all_m<=rem_sample_all;                              
		end if;													 
		end process;												  
end Behavioral;