exchanger1.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    11:39:43 04/22/08
-- Design Name:    
-- Module Name:    exchanger1 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exchanger1 is
	port
	(
	 sw:in std_logic;
	 in1:in integer range 63 downto -63;
	 in2:in integer range 63 downto -63;
	 out1:out integer range 63 downto -63;
	 out2:out integer range 63 downto -63							
	 );
end exchanger1;

architecture Behavioral of exchanger1 is

begin
	process(sw,in1,in2)
		begin
			if sw='1'then
				out1<=in2;
				out2<=in1;
			else
				out1<=in1;
				out2<=in2;
			end if;
	end process;
end Behavioral;