tb_hwtest_decoder.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:   21:26:50 05/04/2008
-- Design Name:   hwtest_decoder
-- Module Name:   tb_hwtest_decoder.vhd
-- Project Name:  BCH_decoder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: hwtest_decoder
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_hwtest_decoder_vhd IS
END tb_hwtest_decoder_vhd;

ARCHITECTURE behavior OF tb_hwtest_decoder_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT hwtest_decoder
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;          
		en_out : OUT std_logic;
		data_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';

	--Outputs
	SIGNAL en_out :  std_logic;
	SIGNAL data_out :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: hwtest_decoder PORT MAP(
		clk => clk,
		reset => reset,
		en_out => en_out,
		data_out => data_out
	);

clk_pro:
	process
		begin
			clk<='1';
			wait for 50ns;
			clk<='0';
			wait for 50ns;
	end process;

reset_pro:
	process
		begin
		reset<='0';
		wait for 500ns;
		reset<='1';
		wait;
	end process;

END;