tb_controller.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:   21:52:30 04/30/2008
-- Design Name:   controller
-- Module Name:   tb_controller.vhd
-- Project Name:  BCH_decoder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: controller
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_controller_vhd IS
END tb_controller_vhd;

ARCHITECTURE behavior OF tb_controller_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT controller
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		ready : IN std_logic;          
		en_all_s : OUT std_logic;
		en_con_s : OUT std_logic;
		en_init_s : OUT std_logic;
		en_load_ps : OUT std_logic;
		en_all_ps : OUT std_logic;
		en_all_euclid : OUT std_logic;
		en_init_euclid : OUT std_logic;
		en_all_sp : OUT std_logic;
		en_init_sp : OUT std_logic;
		en_sel_chien : OUT std_logic;
		en_all_chien : OUT std_logic;
		en_all_correct : OUT std_logic;
		en_read_memory : OUT std_logic;
		en_read_delay : OUT std_logic;
		en_write_delay : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL ready :  std_logic := '0';

	--Outputs
	SIGNAL en_all_s :  std_logic;
	SIGNAL en_con_s :  std_logic;
	SIGNAL en_init_s :  std_logic;
	SIGNAL en_load_ps :  std_logic;
	SIGNAL en_all_ps :  std_logic;
	SIGNAL en_all_euclid :  std_logic;
	SIGNAL en_init_euclid :  std_logic;
	SIGNAL en_all_sp :  std_logic;
	SIGNAL en_init_sp :  std_logic;
	SIGNAL en_sel_chien :  std_logic;
	SIGNAL en_all_chien :  std_logic;
	SIGNAL en_all_correct :  std_logic;
	SIGNAL en_read_memory :  std_logic;
	SIGNAL en_read_delay :  std_logic;
	SIGNAL en_write_delay :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: controller PORT MAP(
		clk => clk,
		reset => reset,
		ready => ready,
		en_all_s => en_all_s,
		en_con_s => en_con_s,
		en_init_s => en_init_s,
		en_load_ps => en_load_ps,
		en_all_ps => en_all_ps,
		en_all_euclid => en_all_euclid,
		en_init_euclid => en_init_euclid,
		en_all_sp => en_all_sp,
		en_init_sp => en_init_sp,
		en_sel_chien => en_sel_chien,
		en_all_chien => en_all_chien,
		en_all_correct => en_all_correct,
		en_read_memory => en_read_memory,
		en_read_delay => en_read_delay,
		en_write_delay => en_write_delay
	);

clk_pro:
	process
	begin
		clk<='1';
		wait for 50ns;
		clk<='0';
		wait for 50ns;
		end process;

reset_pro:
	process
	begin
		reset<='1';
		wait for 700ns;
		reset<='0';
		wait;
		end process;

ready<='1';

END;