hwtest_encode.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    10:29:10 03/24/08
-- Design Name:    
-- Module Name:    hwtest_encode - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hwtest_encode is
	port(
		  clock_top:in std_logic;
		  reset_top:in std_logic;
		  clock_out_top:out std_logic;
		  out_en_top:out std_logic;
		  out_data_top:out std_logic_vector(7 downto 0)
		  );
end hwtest_encode;

architecture Behavioral of hwtest_encode is

component encode
port(
	in_clk:in std_logic;
	in_rst:in std_logic;
	in_en:in std_logic;
	in_data:in std_logic_vector(7 downto 0);
	out_clk:out std_logic;
	out_en:out std_logic;
	out_data:out std_logic_vector(7 downto 0)
);
end component;

component hwtest_data
port(
   addr: IN std_logic_VECTOR(9 downto 0);
	clk: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	en: IN std_logic
);
end component;

signal in_en_tmp:std_logic;
signal in_en_tmp1:std_logic;
signal data_rom:std_logic_vector(7 downto 0);
signal count_top:integer range 511 downto 0;
constant period:integer:=500;
constant period_data:std_logic_vector(9 downto 0):="0111111111";
signal address:std_logic_vector(9 downto 0);
signal nreset:std_logic;
begin

nreset<=not reset_top;

hwtest_data_pro:
			hwtest_data
			port map
			(
			 addr=>address,
			 en=>in_en_tmp,
			 clk=>clock_top,
			 dout=>data_rom
			);

encode_pro:
			encode
			port map
			(
			in_clk=>clock_top,
			in_rst=>nreset,
			in_en=>in_en_tmp1,
			in_data=>data_rom,
			out_clk=>clock_out_top,
			out_en=>out_en_top,
			out_data=>out_data_top
			);

init_pro:
		process(clock_top,reset_top)
		begin
		if(reset_top='0')then
			in_en_tmp<='0';
			in_en_tmp1<='0';
			count_top<=0;
			address<=(others=>'0');
		elsif(clock_top'event and clock_top='1')then
			
			
			in_en_tmp1<=in_en_tmp;		--fifo的使能比rom的使能慢一时钟
			
			if count_top=period then
				--in_en_tmp<=not in_en_tmp;
				count_top<=0;
			elsif count_top<=450 then
					in_en_tmp<='1';
				   count_top<=count_top+1;
			elsif (count_top>450 and count_top<500) then 
			      in_en_tmp<='0';
				   count_top<=count_top+1;
			end if;
         
			if(in_en_tmp='1')then
				
				if address=period_data then
					address<=(others=>'0');
            else
				    address<=address+1;
				end if;
			end if;

		end if;
		end process; 

end Behavioral;