exchanger2.vhd

bch 编码和译码

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    11:41:37 04/22/08
-- Design Name:    
-- Module Name:    exchanger2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exchanger2 is
	port
   	(
		sw:in std_logic;
		in1:in std_logic_vector(12 downto 0);
		in2:in std_logic_vector(12 downto 0);
		out1:out std_logic_vector(12 downto 0);
		out2:out std_logic_vector(12 downto 0)
	 	);
end exchanger2;

architecture Behavioral of exchanger2 is

begin
	process(sw,in1,in2)
		begin
			if sw='1'then
				out1<=in2;
				out2<=in1;
			else
				out1<=in1;
				out2<=in2;
			end if;
	end process;
end Behavioral;