mul6.vhd

bch 编码和译码

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    10:04:25 04/09/08
-- Design Name:    
-- Module Name:    mul6 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul6 is
	port(
		mul6_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul6_out:out std_logic_vector(12 downto 0)
		);
end mul6;

architecture Behavioral of mul6 is

begin

mul6_out(0)<=mul6_in(7);
mul6_out(1)<=mul6_in(8) xor mul6_in(7);
mul6_out(2)<=mul6_in(8) xor mul6_in(9);
mul6_out(3)<=mul6_in(7) xor mul6_in(9) xor mul6_in(10);
mul6_out(4)<=mul6_in(11) xor mul6_in(10) xor mul6_in(8) xor mul6_in(7);
mul6_out(5)<=mul6_in(11) xor mul6_in(9) xor mul6_in(12) xor mul6_in(8);
mul6_out(6)<=mul6_in(12) xor mul6_in(0) xor mul6_in(10) xor mul6_in(9);
mul6_out(7)<=mul6_in(11) xor mul6_in(10) xor mul6_in(1);
mul6_out(8)<=mul6_in(2) xor mul6_in(12) xor mul6_in(11);
mul6_out(9)<=mul6_in(3) xor mul6_in(12);
mul6_out(10)<=mul6_in(4);
mul6_out(11)<=mul6_in(5);
mul6_out(12)<=mul6_in(6);


end Behavioral;