chien2.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    21:33:14 04/09/08
-- Design Name:    
-- Module Name:    chien1 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity chien2 is
port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end chien2;

architecture Behavioral of chien2 is

component mul2
	port(
		mul2_in:in std_logic_vector(12 downto 0);
		mul2_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul4
	port(
		mul4_in:in std_logic_vector(12 downto 0);
		mul4_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul6
	port(
		mul6_in:in std_logic_vector(12 downto 0);
		mul6_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul8
	port(
		mul8_in:in std_logic_vector(12 downto 0);
		mul8_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul10
	port(
		mul10_in:in std_logic_vector(12 downto 0);
		mul10_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul12
	port(
		mul12_in:in std_logic_vector(12 downto 0);
		mul12_out:out std_logic_vector(12 downto 0)
		);
end component;
component mul14
	port(
		mul14_in:in std_logic_vector(12 downto 0);
		mul14_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul16
	port(
		mul16_in:in std_logic_vector(12 downto 0);
		mul16_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul11
	port(
		mul11_in:in std_logic_vector(12 downto 0);
		mul11_out:out std_logic_vector(12 downto 0)
		);
end component;

signal d:std_logic_vector(12 downto 0);
signal product1_tmp:std_logic_vector(12 downto 0);
signal product2_tmp:std_logic_vector(12 downto 0);
signal product3_tmp:std_logic_vector(12 downto 0);
signal product4_tmp:std_logic_vector(12 downto 0);
signal product5_tmp:std_logic_vector(12 downto 0);
signal product6_tmp:std_logic_vector(12 downto 0);
signal product7_tmp:std_logic_vector(12 downto 0);
signal product8_tmp:std_logic_vector(12 downto 0);
signal sel_tmp:std_logic_vector(12 downto 0);
signal err_pol_m:std_logic_vector(12 downto 0);
--signal cnt:integer range 1000 downto 0;
--signal en_sel: std_logic;
begin

d_pro:
	process(clk,reset)
		begin
			if(reset='1')then
				d<=(others=>'0');
			elsif(clk'event and clk='1')then
				if(en_all='1')then
					d<=product8_tmp;
				end if;
			end if;
	end process;

mul11_pro:
		mul11
			port map
			(
			mul11_in=>err_pol,
			mul11_out=>err_pol_m
			);			

sel_pro:
	process(clk)
		begin
			if(en_all='1')then
				if(en_sel='0')then
					sel_tmp<=d;
				else
					sel_tmp<=err_pol_m;
				end if;
			end if;
	end process;

mul2_pro:
	mul2
	port map
	(
	mul2_in=>sel_tmp,
	mul2_out=>product1_tmp
	);

mul4_pro:
	mul4
	port map
	(
	mul4_in=>sel_tmp,
	mul4_out=>product2_tmp
	);

mul6_pro:
	mul6
	port map
	(
	mul6_in=>sel_tmp,
	mul6_out=>product3_tmp
	);

mul8_pro:
	mul8
	port map
	(
	mul8_in=>sel_tmp,
	mul8_out=>product4_tmp
	);

mul10_pro:
	mul10
	port map
	(
	mul10_in=>sel_tmp,
	mul10_out=>product5_tmp
	);

mul12_pro:
	mul12
	port map
	(
	mul12_in=>sel_tmp,
	mul12_out=>product6_tmp
	);

mul14_pro:
	mul14
	port map
	(
	mul14_in=>sel_tmp,
	mul14_out=>product7_tmp
	);	

mul16_pro:
	mul16
	port map
	(
	mul16_in=>sel_tmp,
	mul16_out=>product8_tmp
	);

product1<=product1_tmp;
product2<=product2_tmp;
product3<=product3_tmp;
product4<=product4_tmp;
product5<=product5_tmp;	
product6<=product6_tmp;
product7<=product7_tmp;
product8<=product8_tmp;

--cnt_pro:
--	process(clk,reset)
--		begin
--			if(reset='1')then
--				cnt<=0;
--			elsif(clk'event and clk='1')then
--				if(en_all='1')then
--					if cnt=511 then  -- *
--						cnt<=0;			 --*
--					else
--						cnt<=cnt+1;
--					end if;
--				end if;
--			end if;
--	end process;
--
--
--sel_proc:
--	process(clk)
--		begin
--			if(clk'event and clk='1')then
--				if cnt=0 then			  ---*---
--					en_sel<='1';
--				else
--					en_sel<='0';
--				end if;
--			end if;
--	end process;
													 
end Behavioral;