chien.vhd

bch 编码和译码

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    20:55:14 04/09/08
-- Design Name:    
-- Module Name:    chien - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity chien is
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		out_en:out std_logic;
		err_pol0:in std_logic_vector(12 downto 0);
		err_pol1:in std_logic_vector(12 downto 0);
		err_pol2:in std_logic_vector(12 downto 0);
		err_pol3:in std_logic_vector(12 downto 0);
		err_pol4:in std_logic_vector(12 downto 0);
		err_pol5:in std_logic_vector(12 downto 0);
		err_pol6:in std_logic_vector(12 downto 0);
		err_pol7:in std_logic_vector(12 downto 0);
		err_pol8:in std_logic_vector(12 downto 0);
		err_pol9:in std_logic_vector(12 downto 0);
		err_pol10:in std_logic_vector(12 downto 0);

--sum11:out std_logic_vector(12 downto 0);
--sum12:out std_logic_vector(12 downto 0);
--sum13:out std_logic_vector(12 downto 0);
--sum14:out std_logic_vector(12 downto 0);
--sum15:out std_logic_vector(12 downto 0);
--sum16:out std_logic_vector(12 downto 0);
--sum17:out std_logic_vector(12 downto 0);
--sum18:out std_logic_vector(12 downto 0);
--sum21:out std_logic_vector(12 downto 0);
--sum22:out std_logic_vector(12 downto 0);
--sum23:out std_logic_vector(12 downto 0);
--sum24:out std_logic_vector(12 downto 0);
--sum25:out std_logic_vector(12 downto 0);
--sum26:out std_logic_vector(12 downto 0);
--sum27:out std_logic_vector(12 downto 0);
--sum28:out std_logic_vector(12 downto 0);
--sum31:out std_logic_vector(12 downto 0);
--sum32:out std_logic_vector(12 downto 0);
--sum33:out std_logic_vector(12 downto 0);
--sum34:out std_logic_vector(12 downto 0);
--sum35:out std_logic_vector(12 downto 0);
--sum36:out std_logic_vector(12 downto 0);
--sum37:out std_logic_vector(12 downto 0);
--sum38:out std_logic_vector(12 downto 0);
--sum41:out std_logic_vector(12 downto 0);
--sum42:out std_logic_vector(12 downto 0);
--sum43:out std_logic_vector(12 downto 0);
--sum44:out std_logic_vector(12 downto 0);
--sum45:out std_logic_vector(12 downto 0);
--sum46:out std_logic_vector(12 downto 0);
--sum47:out std_logic_vector(12 downto 0);
--sum48:out std_logic_vector(12 downto 0);
--sum51:out std_logic_vector(12 downto 0);
--sum52:out std_logic_vector(12 downto 0);
--sum53:out std_logic_vector(12 downto 0);
--sum54:out std_logic_vector(12 downto 0);
--sum55:out std_logic_vector(12 downto 0);
--sum56:out std_logic_vector(12 downto 0);
--sum57:out std_logic_vector(12 downto 0);
--sum58:out std_logic_vector(12 downto 0);
--sum61:out std_logic_vector(12 downto 0);
--sum62:out std_logic_vector(12 downto 0);
--sum63:out std_logic_vector(12 downto 0);
--sum64:out std_logic_vector(12 downto 0);
--sum65:out std_logic_vector(12 downto 0);
--sum66:out std_logic_vector(12 downto 0);
--sum67:out std_logic_vector(12 downto 0);
--sum68:out std_logic_vector(12 downto 0);
--  sum71:out std_logic_vector(12 downto 0);
--  sum72:out std_logic_vector(12 downto 0);
--  sum73:out std_logic_vector(12 downto 0);
--  sum74:out std_logic_vector(12 downto 0);
--  sum75:out std_logic_vector(12 downto 0);
--  sum76:out std_logic_vector(12 downto 0);
--  sum77:out std_logic_vector(12 downto 0);
--  sum78:out std_logic_vector(12 downto 0);
--  sum81:out std_logic_vector(12 downto 0);
--  sum82:out std_logic_vector(12 downto 0);
--  sum83:out std_logic_vector(12 downto 0);
--  sum84:out std_logic_vector(12 downto 0);
--  sum85:out std_logic_vector(12 downto 0);
--  sum86:out std_logic_vector(12 downto 0);
--  sum87:out std_logic_vector(12 downto 0);
--  sum88:out std_logic_vector(12 downto 0);
--  sum91:out std_logic_vector(12 downto 0);
--  sum92:out std_logic_vector(12 downto 0);
--  sum93:out std_logic_vector(12 downto 0);
--  sum94:out std_logic_vector(12 downto 0);
--  sum95:out std_logic_vector(12 downto 0);
--  sum96:out std_logic_vector(12 downto 0);
--  sum97:out std_logic_vector(12 downto 0);
--  sum98:out std_logic_vector(12 downto 0);
--  sum101:out std_logic_vector(12 downto 0);
--  sum102:out std_logic_vector(12 downto 0);
--  sum103:out std_logic_vector(12 downto 0);
--  sum104:out std_logic_vector(12 downto 0);
--  sum105:out std_logic_vector(12 downto 0);
--  sum106:out std_logic_vector(12 downto 0);
--  sum107:out std_logic_vector(12 downto 0);
--  sum108:out std_logic_vector(12 downto 0);

		sum1:out std_logic_vector(12 downto 0);
		sum2:out std_logic_vector(12 downto 0);
		sum3:out std_logic_vector(12 downto 0);
		sum4:out std_logic_vector(12 downto 0);
		sum5:out std_logic_vector(12 downto 0);
		sum6:out std_logic_vector(12 downto 0);
		sum7:out std_logic_vector(12 downto 0);
		sum8:out std_logic_vector(12 downto 0)
	);
end chien;

architecture Behavioral of chien is
component chien1
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien2
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien3
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien4
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien5
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien6
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien7
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien8
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien9
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

component chien10
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end component;

signal sum11_t:std_logic_vector(12 downto 0);
signal sum12_t:std_logic_vector(12 downto 0);
signal sum13_t:std_logic_vector(12 downto 0);
signal sum14_t:std_logic_vector(12 downto 0);
signal sum15_t:std_logic_vector(12 downto 0);
signal sum16_t:std_logic_vector(12 downto 0);
signal sum17_t:std_logic_vector(12 downto 0);
signal sum18_t:std_logic_vector(12 downto 0);
signal sum21_t:std_logic_vector(12 downto 0);
signal sum22_t:std_logic_vector(12 downto 0);
signal sum23_t:std_logic_vector(12 downto 0);
signal sum24_t:std_logic_vector(12 downto 0);
signal sum25_t:std_logic_vector(12 downto 0);
signal sum26_t:std_logic_vector(12 downto 0);
signal sum27_t:std_logic_vector(12 downto 0);
signal sum28_t:std_logic_vector(12 downto 0);
signal sum31_t:std_logic_vector(12 downto 0);
signal sum32_t:std_logic_vector(12 downto 0);
signal sum33_t:std_logic_vector(12 downto 0);
signal sum34_t:std_logic_vector(12 downto 0);
signal sum35_t:std_logic_vector(12 downto 0);
signal sum36_t:std_logic_vector(12 downto 0);
signal sum37_t:std_logic_vector(12 downto 0);
signal sum38_t:std_logic_vector(12 downto 0);
signal sum41_t:std_logic_vector(12 downto 0);
signal sum42_t:std_logic_vector(12 downto 0);
signal sum43_t:std_logic_vector(12 downto 0);
signal sum44_t:std_logic_vector(12 downto 0);
signal sum45_t:std_logic_vector(12 downto 0);
signal sum46_t:std_logic_vector(12 downto 0);
signal sum47_t:std_logic_vector(12 downto 0);
signal sum48_t:std_logic_vector(12 downto 0);
signal sum51_t:std_logic_vector(12 downto 0);
signal sum52_t:std_logic_vector(12 downto 0);
signal sum53_t:std_logic_vector(12 downto 0);
signal sum54_t:std_logic_vector(12 downto 0);
signal sum55_t:std_logic_vector(12 downto 0);
signal sum56_t:std_logic_vector(12 downto 0);
signal sum57_t:std_logic_vector(12 downto 0);
signal sum58_t:std_logic_vector(12 downto 0);
signal sum61_t:std_logic_vector(12 downto 0);
signal sum62_t:std_logic_vector(12 downto 0);
signal sum63_t:std_logic_vector(12 downto 0);
signal sum64_t:std_logic_vector(12 downto 0);
signal sum65_t:std_logic_vector(12 downto 0);
signal sum66_t:std_logic_vector(12 downto 0);
signal sum67_t:std_logic_vector(12 downto 0);
signal sum68_t:std_logic_vector(12 downto 0);
signal sum71_t:std_logic_vector(12 downto 0);
signal sum72_t:std_logic_vector(12 downto 0);
signal sum73_t:std_logic_vector(12 downto 0);
signal sum74_t:std_logic_vector(12 downto 0);
signal sum75_t:std_logic_vector(12 downto 0);
signal sum76_t:std_logic_vector(12 downto 0);
signal sum77_t:std_logic_vector(12 downto 0);
signal sum78_t:std_logic_vector(12 downto 0);
signal sum81_t:std_logic_vector(12 downto 0);
signal sum82_t:std_logic_vector(12 downto 0);
signal sum83_t:std_logic_vector(12 downto 0);
signal sum84_t:std_logic_vector(12 downto 0);
signal sum85_t:std_logic_vector(12 downto 0);
signal sum86_t:std_logic_vector(12 downto 0);
signal sum87_t:std_logic_vector(12 downto 0);
signal sum88_t:std_logic_vector(12 downto 0);
signal sum91_t:std_logic_vector(12 downto 0);
signal sum92_t:std_logic_vector(12 downto 0);
signal sum93_t:std_logic_vector(12 downto 0);
signal sum94_t:std_logic_vector(12 downto 0);
signal sum95_t:std_logic_vector(12 downto 0);
signal sum96_t:std_logic_vector(12 downto 0);
signal sum97_t:std_logic_vector(12 downto 0);
signal sum98_t:std_logic_vector(12 downto 0);
signal sum101_t:std_logic_vector(12 downto 0);
signal sum102_t:std_logic_vector(12 downto 0);
signal sum103_t:std_logic_vector(12 downto 0);
signal sum104_t:std_logic_vector(12 downto 0);
signal sum105_t:std_logic_vector(12 downto 0);
signal sum106_t:std_logic_vector(12 downto 0);
signal sum107_t:std_logic_vector(12 downto 0);
signal sum108_t:std_logic_vector(12 downto 0);
signal sum1_tmp:std_logic_vector(12 downto 0);
signal sum2_tmp:std_logic_vector(12 downto 0);
signal sum3_tmp:std_logic_vector(12 downto 0);
signal sum4_tmp:std_logic_vector(12 downto 0);
signal sum5_tmp:std_logic_vector(12 downto 0);
signal sum6_tmp:std_logic_vector(12 downto 0);
signal sum7_tmp:std_logic_vector(12 downto 0);
signal sum8_tmp:std_logic_vector(12 downto 0);

signal cnt_all:integer range 1000 downto 0;

begin

chien1_pro:
	chien1
	port map
	(
	 	clk=>clk,
		reset=>reset,
		en_all=>en_all,
		en_sel=>en_sel,
		err_pol=>err_pol1,
		product1=>sum11_t,
		product2=>sum12_t,
		product3=>sum13_t,
		product4=>sum14_t,
		product5=>sum15_t,
		product6=>sum16_t,
		product7=>sum17_t,
		product8=>sum18_t