fre_hwtest_decoder.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    16:49:43 05/05/08
-- Design Name:    
-- Module Name:    fre_hwtest_decoder - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fre_hwtest_decoder is
	port	
		(
		  clk:in std_logic;
		  reset:in std_logic;
		  en_out:out std_logic;
		  data_out:out std_logic_vector(7 downto 0)
			);
end fre_hwtest_decoder;

architecture Behavioral of fre_hwtest_decoder is

component hwtest_decoder 
		port(
		  clk:in std_logic;
		  reset:in std_logic;
		  en_out:out std_logic;
		  data_out:out std_logic_vector(7 downto 0)
		  );
end component;

component dcm1
	 port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKFX_OUT       : out   std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic
			 );
end component;

signal  clk_div:std_logic;
signal  reset_dcm:std_logic;
signal  nreset:std_logic;

begin

hwtest_decoder_pro:
	hwtest_decoder
		port map
		(
		  clk=>clk_div,
		  reset=>reset_dcm,
		  en_out=>en_out,
		  data_out=>data_out
		);

dcm1_pro:
	dcm1
	port map
	(
	       CLKIN_IN =>clk,
          RST_IN=>nreset,
          CLKFX_OUT=>clk_div,
          CLKIN_IBUFG_OUT=>open, 
          CLK0_OUT=>open,
          LOCKED_OUT=>reset_dcm	
	);

nreset<=not reset;

end Behavioral;